Search found 140 matches

by Alyosha_TAS
Fri Jan 14, 2022 5:37 am
Forum: NESemdev
Topic: Count Errors Test ROM and some new DMC glitch info
Replies: 56
Views: 2691

Re: Count Errors Test ROM and some new DMC glitch info

I see, interesting architectural difference there, thanks for the replies.
by Alyosha_TAS
Thu Jan 13, 2022 4:18 pm
Forum: NESemdev
Topic: Count Errors Test ROM and some new DMC glitch info
Replies: 56
Views: 2691

Re: Count Errors Test ROM and some new DMC glitch info

Yikes, I definitely can't account for that with the current architecture I have, time to start rethinking things I guess. Even if irrelevantall to real world work loads, I welcome all emulator breaking test ROMs. i do have a question though, if it's always the cpu address on the bus except for the r...
by Alyosha_TAS
Sun Jan 09, 2022 4:25 pm
Forum: NESemdev
Topic: Count Errors Test ROM and some new DMC glitch info
Replies: 56
Views: 2691

Re: Count Errors Test ROM and some new DMC glitch info

Neat game, but yeah no TAS. Unfortunately most existing TASes desync pretty badly on the updated emulator and I don't have time to make entirely new ones. Looks like my own testing will be slowing down significantly for now (but I think we got nearly all the important cases anyway.) I'll need to com...
by Alyosha_TAS
Sat Jan 08, 2022 3:55 pm
Forum: NESemdev
Topic: Count Errors Test ROM and some new DMC glitch info
Replies: 56
Views: 2691

Re: Count Errors Test ROM and some new DMC glitch info

Yes that it what I am doing for branch. I got confused because normal instructions check for interrupts, but that case is written to check for the absence of interrupts. I should probably change things to be uniform. SMB3 works correctly in this way. Actually, there are no longer any TASes I have th...
by Alyosha_TAS
Fri Jan 07, 2022 6:21 am
Forum: NESemdev
Topic: Count Errors Test ROM and some new DMC glitch info
Replies: 56
Views: 2691

Re: Count Errors Test ROM and some new DMC glitch info

Actually forget that stuff I had written about branch and DMA (I already removed it) I was just confusing which conditions are being checked, nothing unusual is happening there. I'm pretty certain any delay in the DMA event (the actual read) is two cycles. The Halt always occurs as soon as the write...
by Alyosha_TAS
Thu Jan 06, 2022 8:14 pm
Forum: NESemdev
Topic: Count Errors Test ROM and some new DMC glitch info
Replies: 56
Views: 2691

Re: Count Errors Test ROM and some new DMC glitch info

I can try. First of all to avoid confusion, whenever I say cycles I always mean CPU cycles. NESHawk doesn't have an independent concept of APU cycles. So when I have a 2-cycle delay, it's one APU cycle. Ok, so first of all, for buffer empty / refill, I believe the timing is the same as for the 4 cyc...
by Alyosha_TAS
Thu Jan 06, 2022 11:24 am
Forum: NESemdev
Topic: Count Errors Test ROM and some new DMC glitch info
Replies: 56
Views: 2691

Re: Count Errors Test ROM and some new DMC glitch info

Well I fixed the edge case in 3 consecutive writes handling but it didn't make a difference, I suppose that case just wasn't encountered. Still a good catch though. For TASes that only use one controller, only one controller is connected to the replay device, the other port is open, so that's not an...
by Alyosha_TAS
Thu Jan 06, 2022 6:24 am
Forum: NESemdev
Topic: Count Errors Test ROM and some new DMC glitch info
Replies: 56
Views: 2691

Re: Count Errors Test ROM and some new DMC glitch info

To change controllers, after you load a NES rom an 'NES' menu will appear in the top row of menues,click that and go to controller settings to change them. I'm confident attached / unattached controllers behave correctly, but you kow what, there just might be a case where the 3 consecutive writes ar...
by Alyosha_TAS
Wed Jan 05, 2022 8:48 pm
Forum: NESemdev
Topic: Count Errors Test ROM and some new DMC glitch info
Replies: 56
Views: 2691

Re: Count Errors Test ROM and some new DMC glitch info

Cool, so at the very least it seems to not be an analog effect on individual consoles, that's reassuring. Even after I implemented everything learned so far, I still have a consistent desync in Super Mario Bros 3. I also have no further ideas of missing edge cases. The game doesn't use DMC IRQ, the ...
by Alyosha_TAS
Wed Jan 05, 2022 6:55 pm
Forum: NESemdev
Topic: Count Errors Test ROM and some new DMC glitch info
Replies: 56
Views: 2691

Re: Count Errors Test ROM and some new DMC glitch info

Is there a console that got 4 cycle blips with the old test and not the new test?
by Alyosha_TAS
Wed Jan 05, 2022 6:07 am
Forum: NESemdev
Topic: Count Errors Test ROM and some new DMC glitch info
Replies: 56
Views: 2691

Re: Count Errors Test ROM and some new DMC glitch info

Just to make sure I understand your results correctly, have you ever gotten different results for the 4-cycle blips on the same condole?
by Alyosha_TAS
Mon Jan 03, 2022 2:46 pm
Forum: NESemdev
Topic: Count Errors Test ROM and some new DMC glitch info
Replies: 56
Views: 2691

Re: Count Errors Test ROM and some new DMC glitch info

Awesome! These tests are exactly what I needed, thanks a lot! On my console: explicit test: pass implicit test: fail, only two 1's in their expected positions. no 4's. I did 10 power cycles and 10 resets. Emulator: After implementing these cases and the IRQ delay mentioned above, Time Lord TAS now w...
by Alyosha_TAS
Sat Jan 01, 2022 5:02 pm
Forum: NESemdev
Topic: Count Errors Test ROM and some new DMC glitch info
Replies: 56
Views: 2691

Re: Count Errors Test ROM and some new DMC glitch info

Attached is a test ROM that demonstrates the delay between DMC DMA and IRQ execution. It uses the value stored in the Y register to set the volume of the pulse channel that is enabled in the IRQ handler. Y has a value for 0 volume before DMA, then the following instrucitons occur: STA $4015 (enable ...
by Alyosha_TAS
Wed Dec 29, 2021 11:50 am
Forum: NESemdev
Topic: Count Errors Test ROM and some new DMC glitch info
Replies: 56
Views: 2691

Re: Count Errors Test ROM and some new DMC glitch info

Following up on the fact that IRQ occurs a few cycles after DMA finishes, it turns out you can cancel an IRQ by writing to $4010 in between the time the DMA finishes and the IRQ occurs (checked in visual NES.) Not yet sure about other effects like enabling and the loop flag. I'll check disabling via...
by Alyosha_TAS
Sun Dec 26, 2021 11:02 am
Forum: NESemdev
Topic: Count Errors Test ROM and some new DMC glitch info
Replies: 56
Views: 2691

Re: Count Errors Test ROM and some new DMC glitch info

Another new finding. NMI timing is effected by DMA. Blargg's test 4-irq_and_dma.nes demonstrated this already for IRQ's but the same seems to be true for NMI as well. (Basically, an IRQ will be recognized if it occurs on the first cycle that the DMA starts, but will otherwise be delayed by one cycle...