Search found 318 matches

by Fiskbit
Thu Jan 27, 2022 1:37 am
Forum: Web Issues
Topic: Great job! No spam topics in a while!
Replies: 2
Views: 111

Re: Great job! No spam topics in a while!

Spam actually started up again right away when the forums were reopened, but various features we're using now have really helped. There are still a few spammers who manage to register and post, but because new user posts now require approval, even those get blocked from general view.
by Fiskbit
Wed Jan 19, 2022 7:13 am
Forum: NESdev
Topic: Glitch-free controller reads with DMC?
Replies: 65
Views: 74179

Re: Glitch-free controller reads with DMC?

Another wrinkle: DMC DMA landing at the end of OAM DMA only takes 1 or 3 cycles, immediately breaking sync and causing problems for synced read functions longer than one DMC period. Aligned write cycles alone do not solve this case. This is also relevant for the EPSM , where CPU/APU sync is required...
by Fiskbit
Thu Jan 13, 2022 5:19 pm
Forum: NESemdev
Topic: Count Errors Test ROM and some new DMC glitch info
Replies: 56
Views: 2691

Re: Count Errors Test ROM and some new DMC glitch info

Note that because CPU/APU alignment is random on power-on, that test isn't guaranteed on the first pass to have DMC DMA occur during OAM DMA, but will settle into the desired arrangement forevermore afterward.
by Fiskbit
Thu Jan 13, 2022 1:27 am
Forum: NESemdev
Topic: Count Errors Test ROM and some new DMC glitch info
Replies: 56
Views: 2691

Re: Count Errors Test ROM and some new DMC glitch info

lidnariq took some measurements today on a simple test ROM and found the when DMC DMA interrupts OAM DMA, the address on the bus on the OAM DMA alignment cycle before accesses resume is the CPU address. It seems that every halted cycle where DMA is not actively accessing uses the CPU address. I shou...
by Fiskbit
Mon Jan 10, 2022 4:30 pm
Forum: NESemdev
Topic: Count Errors Test ROM and some new DMC glitch info
Replies: 56
Views: 2691

Re: Count Errors Test ROM and some new DMC glitch info

The timing on rereads of $2007 can also matter, since during rendering, it does increments on fine y and coarse x, which could affect sprite 0 timing. (I guess it could also matter for something like A12 edge detection outside of rendering.) Aside from situations caused by bugs, I don't know if this...
by Fiskbit
Mon Jan 10, 2022 3:48 pm
Forum: NES Hardware and Flash Equipment
Topic: Need advice buying a NES-101 and a flash cart
Replies: 39
Views: 1234

Re: Need advice buying a NES-101 and a flash cart

The one major Game Genie limitation is that on carts that map below $8000, you'll get bus conflicts between cart addresses that match in the low 15 bits. You'll want to put your reset vector at $7FFA-7FFB, as well, so they don't conflict.
by Fiskbit
Mon Jan 10, 2022 1:55 pm
Forum: NES Hardware and Flash Equipment
Topic: Need advice buying a NES-101 and a flash cart
Replies: 39
Views: 1234

Re: Need advice buying a NES-101 and a flash cart

With a Game Genie, you should be able to just override the reset vector.
by Fiskbit
Mon Jan 10, 2022 10:00 am
Forum: NES Hardware and Flash Equipment
Topic: Need advice buying a NES-101 and a flash cart
Replies: 39
Views: 1234

Re: Need advice buying a NES-101 and a flash cart

The Zelda ACE only applies to the FDS version. The game doesn't overwrite save files (if the checksums match) or the last page of SRAM.

Loading code in this way does give you access to real mappers, but doesn't give you access to power-on timings and state.
by Fiskbit
Mon Jan 10, 2022 9:05 am
Forum: NES Hardware and Flash Equipment
Topic: Need advice buying a NES-101 and a flash cart
Replies: 39
Views: 1234

Re: Need advice buying a NES-101 and a flash cart

Zelda copies code to RAM at startup, overwriting whatever you put there. You've gotten a perfectly good suggestion about buying a flashable cartridge and an adapter; is that not workable for some reason?
by Fiskbit
Sat Jan 08, 2022 4:33 pm
Forum: NESemdev
Topic: Count Errors Test ROM and some new DMC glitch info
Replies: 56
Views: 2691

Re: Count Errors Test ROM and some new DMC glitch info

Was about to post both of those, but was checking some other Codemasters games to see if I could find others. Not sure if it's useful because I can't imagine it has a TAS, but I used it in Atmo Sphere.
by Fiskbit
Fri Jan 07, 2022 4:44 pm
Forum: NESemdev
Topic: Count Errors Test ROM and some new DMC glitch info
Replies: 56
Views: 2691

Re: Count Errors Test ROM and some new DMC glitch info

Thanks, that mostly clears up my confusion; I've been referring to delays with regard to the halting cycle, not the DMA read cycle. While a write cycle will always cause the halt to delay by 1 CPU cycle, it doesn't always cause a delay in the DMA itself. For a reload DMC DMA, landing on 1 write cycl...
by Fiskbit
Fri Jan 07, 2022 12:06 am
Forum: NESemdev
Topic: Count Errors Test ROM and some new DMC glitch info
Replies: 56
Views: 2691

Re: Count Errors Test ROM and some new DMC glitch info

Thanks, I think that makes enough sense. I'll see about getting a more complete suite of pass/fail tests for all this stuff over the next while. Would be good to move the visual tests from dmc_dma_start_test_v2 to something automatic, as well, like verifying that 1-cycle blips are skipped if they la...
by Fiskbit
Thu Jan 06, 2022 5:33 pm
Forum: NESemdev
Topic: Count Errors Test ROM and some new DMC glitch info
Replies: 56
Views: 2691

Re: Count Errors Test ROM and some new DMC glitch info

Would you be willing to write out a cycle-by-cycle breakdown of the edge cases you've identified lately? Specifically, this branch/interrupt/DMA case, the DMC IRQ timing, and the buffer empty/refill? With that, I can try to puzzle out pass/fail test ROMs for the various effects. I've also been a lit...
by Fiskbit
Thu Jan 06, 2022 6:43 am
Forum: NESemdev
Topic: Count Errors Test ROM and some new DMC glitch info
Replies: 56
Views: 2691

Re: Count Errors Test ROM and some new DMC glitch info

DMA cannot halt on write cycles and should just keep being delayed one cycle at a time, so my expectation is that a 3-cycles-later DMA should be delayed 3 times and take 4 cycles, while a 4-cycles-later one should only be delayed twice and still take 3 cycles. This should be testable, though I'm not...
by Fiskbit
Thu Jan 06, 2022 1:09 am
Forum: NESdev
Topic: Is there any device or dumper out to dump my old famicom multi carts
Replies: 3
Views: 291

Re: Is there any device or dumper out to dump my old famicom multi carts

I've successfully used the INLretro to dump numerous carts and it does a pretty good job. For a random multicart, though, there probably isn't already a script that knows how to dump it, so you'll need to modify an existing one or add a new one. If you can find a description of the hardware, this sh...