nesdev.org

A compiler can have intimate knowledge of how to order instructions so that various latencies inside modern CPUs won't add up but get overlapped instead. I know I'll be able to beat a compiler when writing 486 and Pentium code since there's very little that gets in the way but with a P4 and most cu...

Maybe this is due to me being biased (even after learning C and much of C++), but I find this difficult to believe. I don't see how a compiler could generate more efficient code when it has no real intuition of how any specific program operates, and (at least for what I've seen for x86), function c...

Though honestly, this entire problem only happens with division. That and the general trend of newer versions of C and C++ compilers becoming more pedantic about treating signed overflow and other undefined behaviors as an excuse to make unexpectedly aggressive optimizations. Raymond Chen has refer...

If one wanted to use OAM-DMA to feed data that would be meaningless to the OAM and then later send meaningful data, that would be possible, but one would lose the ability to extend the "useful" part of vblank by disabling background rendering and ensuring that no sprites are too high on t...

Assuming that it's a pretty common problem, and that it's impossible to teach C programmers not to use signed numbers... it would almost make sense to implement a "shift-and-round-towards-zero" opcode in newer processors (the newer ARM CPUs do actually have a fairly useless "uxt"...

Hijacking OAMDMA is guaranteed to safely handle any analog timing issues, because it's only running at the same data rate as the CPU, not twice the rate as the CPU. I was under the impression that the weird controller-port interactions with DMA were caused by the fact that DMA cycles didn't use the...

One possibility is OAM DMA twice during vblank: once with the data to send to the pseudo-dual-port video memory on the cartridge, and again with the actual data to send to OAM. This way, CPU A7-A0 could act as the counter, and the cart would snoop the first DMA to transfer one byte per two cycles. ...

It sounds interesting, if it can work. What concerns me is that I don't think you can safely rely on the address lines being stable early, from discussions I've had with kevtris (while he was designing the Hi-Def NES), the address lines and M2 are going to be problematic if you want to be compatibl...

jsr springBoard ; Copy 256 bytes of data from data banked at $6xxx while running code at $7Fxx Oh, the ZX80 trick. Read the byte in the first half, replace it with something else (a 1-cycle NOP there, a NOP-slide here) as long as it's strictly in-order and no bytes are refetched... I wonder if ther...

I vaguely remember there being a lot of bus capacitance here. When we were doing the initial research on the VRC6's extended nametable modes, I remember asking BootGod to solder eight resistors (10k) in lieu of the ROM and NTRAM, from (VRC6 CHR ROM A10..A15 and VRC6 CHR ROM /CE and VRC6 NTRAM /CE) ...

I'm sure this has probably been covered before, but wanted to share anyway. I was really surprised to see that this uses roughly half as many cycles, for just a handful of extra bytes of code. I understood in theory that a loop which makes 256 comparisons would take more cycles that a loop that onl...

a 74HC373 that would take input from the CPU-side data bus and output onto the PPU-side data bus. The PPU drives the AD0..7 pins continuously at every single moment that it is not itself asserting /RD. See Visual2C02 transistors t16479, t16501, t16516, t16511, and t16534. Continuing my last point: ...

a 74HC373 that would take input from the CPU-side data bus and output onto the PPU-side data bus. The PPU drives the AD0..7 pins continuously at every single moment that it is not itself asserting /RD. See Visual2C02 transistors t16479, t16501, t16516, t16511, and t16534. I'd been planning on separ...

For a traditional design this is true. But if you want to get fancy and take advantage of the level shifters and actually make them work for you, the 39 i/o may just be enough. I've got a time multiplexed 'dual port' design I'm prototyping on right now that only requires 53 gpio and has full PPU/CP...

My opinion is that bit shifting only makes sense for unsigned numbers. Bit shifting signed numbers left is equivalent to multiplication in cases where the arithmetical value of the product would fit in the result type. Bit shifting of signed numbers right is equivalent to floored division. In what ...