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You still have to generate the synchronization i.e. there's still no magic to restart the FIFO. Synchronization only needs to happen once-- ever --if one never lets the DMC run dry. Individual IRQ responses may have up to 7 cycles of uncertainty, depending upon the longest opcode that may be runnin...

Most of the approaches I've seen described for using DMC interrupts for raster timing require compensation for some rather large timing uncertainties. From what I can tell, at least on MESEN and my own console, there's a much easier and more efficient technique. I haven't figured out the best way to...

dougeff, your description completely omits the compensation for the APU-PPU desynchronization, which is the "heart" of this technique. Without this compensation, there's not nearly enough precision to do raster effects (the time at which the IRQ fired can vary by up to 4 scanlines). This ...

Can anybody please tell me how a proper comparison of an unsigned int variable with a constant value (that is also in the range of unsigned int) has to look like in assembly, so that I can write it in inline assembly? There are a number of optimal variations for different constant values. For (cons...

i just wrote a little table-driven test which uses DMC interrupts to produce raster splits at mostly-eight-line intervals. For purposes of this demo, the raster IRQ simply changes the RGB emphasis bits (as as to make the effects visible in the screen borders) and all stores occur the same amount of ...

Also if you wait long enough things that everybody implements anyway do usually eventually make it into the standard spec . Only if it's something that the authors of the Standard hadn't expected to be supported by any compiler writers who weren't being deliberately obtuse. Unfortunately, the autho...

BUT IT DIDN'T WORK! I watched the Q0~Q3 of 74'161 using LEDs to show the status and noticed that: 1. Data latched successfully. 2. Once switched to the selected game, data on Q0~Q3 disappeared immediately(all 0). Then the game crashed. Removed the OR gate and tried again: 1. Data latched successful...

They didn't really reevaluate what they were doing after the Famicom; they just stuck an extra 10 pins on to subsume the FDS cable, and another 4 for the CIC. There's lots of little things that seem obvious in hindsight that would have either saved money or simplified certain things afterwards. Add...

It'll delay reads from and writes to RAM by a little bit. If there's a glitch because /ROMSEL arrives later than M2, and that glitch causes an erroneous write to RAM when the game tries to set the IRQ, then the capacitor might help with that. Slower RAMs should also work. I wonder why the NES decid...

I think the cases where people even try to hand-write assembly, and to optimize it, are now so rare that basically no engineers are able to do that anymore. The performance gain is not just the code but the time it takes to actually hand-write highly performing assembly code. In the industry it's n...

The signal on /LOAD needs to become valid after the signal on CLK, so I think you have the roles of /PPUWR and PPUA13 reversed. While what you drew could work, it would preclude the use of CHRAM. I think I'd favor triggering on addresses in the range $3000-$3FFF. If you're only using this thing for ...

i think if the incoming ID to the subroutine is #0 or otherwise has no modulo left from AND #7, a BNE would have the Y-loop wrap around for 255 more iterations. [ There are two approaches one can take here: plan on the loop running 1-8 times, or handle the zero-case specially and then have it loop ...

I think that's a very small part of programming though; and even then, you could write assembly macros that would generate the optimum code for the needed array size. If you decide to change the array size, there's no need to re-write the code that calls the macros. I've had macro definitions that ...

I suspect the idea that compilers can outperform handwritten assembly comes from modern 32- and 64-bit multi-core high-end processors that have super-complex instructions, deep pipelines that must be kept full, multi-level cache, out-of order execution, and things that simply don't apply to the 650...

Your code looks fine to me. I'd be tempted to replace the loop with a lookup table, which would be faster and I think might be clearer, but it shouldn't matter. I don't think dey affects condition flags, so the loop exit condition is wrong. Also, if y holds a value 0 to 7 and the accumulator holds ...