nesdev.org

Ruslansh wrote:Chip and Dale works without problems

What do you mean?

using 5-bit shit register What kind of register is that? o_O What do you mean by "what kind"? A shift register, to build a parallel output from a serial input. As MMC1 internal registers are 5 bit wide, the shit register must be 4 bit (if using a state machine to generate load control sig...

You should be able to further shrink the number of macrocells required by combining the state machine into the shift register, as tepples and I outlined here . My approach was not to fully optimize the design, with somekind of commercial mind, but try to make it very clear, more with an educational...

How many macrocells would a subset supporting only 8K CHR ROM switching (no CHR mode bit in $8000, no $C000 at all) take? That'd be a useful subset to get SNROM/SUROM/SXROM going. Interesting cutdown here :shock: It seems that such a MMC1 would fit in the smaller XC9536 CPLD, as it requires only 33...

I just released the source code of a MMC1 clone, which I just finished testing on real hardware. It is well structured and commented, to allow anyone curious to look at it. Posted in this forum: http://forums.nesdev.com/viewtopic.php?f=9&t=10010 MMC1 is not complex, as it has been said, but it r...

I just finished developing a MMC1 mapper clone, running successfully on a Xilinx XC9572 CPLD and a SNROM PCB (Kid Icarus/Metroid). All features are supported except 32 kb PGR ROM bank size. WRAM write can be enabled and disabled at any time (starts in enable state) Mapper powers-up with all register...

Soy David Senabre, autor de la web y los artículos de consolas para siempre, y sólo quería comentar que la página está completamente operativa. Puede que los problemas que se comentaban aquí se deban a que coincidió con unos días que nos quedamos sin servidor.
Un saludo

No, all clear, thanks

Yes, I will try that dissasembler and see how it works.
I was using NES Disassembler v1.0 beta4, that works fairly well, but still misses things.

Hello!
I understand almost all about copyNES hardware, but looking into the schematics, I can't see how it can upload data to WRAM in order for the NES to run it.
I see no conection between the I/O chip and the WRAM, maybe it is missed in the drawing??
Anyone knows??

Thank you.

Hello!
I'm working on dissasembling a game, and I want to reassemble it.
I have dissasembled bank 7, last one (it is an 8 banks ROM).
But I know no way of reassemble the whole game.
Anyone knows??
Thank you.