nesdev.org

EDIT3: I came up with a suitable circuit on paper which trades off speed for simplicity. It's made with extremely common chips and only emulates a 2Kx16 bit ROM, as well as provide a SNES R/W interface (PC decoded /ROMSEL). The chips are currently: 3x74374, 3x74157, 1x7400, 2x74244, 2x6116/6264, ma...

If the ROM data has already been entirely decompressed, what's the point? Having the decompressed data *only* allow us to play the game, not to really *emulate* how the physical thing works. And that's the holy grial of emulation, after all... Of course, you can also count with the intellectual cha...

other unknown things related to SNES emulation, like whether the S-DSP has a processor or is all hardware. If someone has a broken SNES (or a spare they don't care if I break), I can decap the chip and probably answer this. It is even possible that I could read out the ROM inside of this (assuming ...

I misspoke. Oh god, kill him xD. There's a bit more bickering going on here than is comfortable for a topic that should be friendly collaboration. May I please request that everyone stop pouncing on mistakes and focus on the fun of reverse engineering this beast? Hehe no worries, that was actually ...

I misspoke. Oh god, kill him xD. GDSF7?! This outline is ridiculous, the system only needs TWO small ROM emulators, one for each SPC bus. The ROM emulator which stores the SNES code also stores the results. BOTH emulators can be connected to the SAME parallel port. Yep true. But then again, you hav...

Of course the device is bidirectional, as I wrote initially I think the best plan of attack is to upload SPC data ROM, run a program on SNES which dumps decrypted data to the other RAM, which is then read back by the PC. Because the ROM emulator can reset the SNES, this can be entirely automated (t...

Do you plan on building a ROM emulator for this project? I've designed an 8/16-bit ROM emulator (13x 74 series chips - $5.50), and I could turn it into a dual ROM emulator and add an EPP interface but it'd be a big chore so I'd only do it if you're serious. Perhaps I explained myself wrong. I don't...

A-1 is "address negative 1", because it's one bit lower than A0 which selects a WORD on a 16-bit ROM. When a 16-bit ROM can be put into 8-bit mode (/BYTE signal), D15 generally becomes an input which selects which byte of the word is output on D0-7. This is why in the document you mention...

kammedo, D15 on a 8/16-bit ROM is A-1 or 8-bit A0. Where are the SPC7110 schematics? All I see is previously published pinouts. Don't recall having stated they would be original. Schematics are underway, need to get a proper software to make them *yahwn*. Anyone is able to track them down with a si...

I posted my work on the ynt site :

www.yntproject.net?section=docs - check the SPC7110 pinouts.
Also, I have the doc from TheDumper about the GDSF header somewhere. Will put it up when I find it.

tepples wrote:The name "SPC" is in both SPC700 (Super NES sound CPU) and SPC7110 (data decompression IC). Is there a
reason for this?

Not that i recall at least..

I have been researching about that alot, considering quite a few solutions. I even managed to get Charles MacDonald to work on FEoEZ, but the project stopped mainly due to time lacking. The best solution I've come up with is a U2 (was it U2 or another?) chip - USB 2.0 interface. That would be the le...