nesdev.org

2000 cycle delay might have had something to do with the initial values of the channels' timers . Hmm, that would actually make a lot of sense since the timer is just a divider based off of the CPU clock and it can take quite a few CPU clock cycles before the first APU clock "tick" is eve...

Tooth fairies exist, but a tooth fairy is just a DDS who happens to be gay.

LOLOLOL - Tepples is too funny!

My NES emulator uses an RGB display driver. It works really well - as far as I can tell. Are there certain things I should be doing (or can do) to make the colors more realistic since I'm not using a composite video signal like the original NES? EDIT: Btw, my video driver does not use any of the clo...

WHAT?! There's no tooth fairy?!?!?!?!? :'(



LOL, but in all seriousness, a "Myths" section would be very useful.

So it turns out kyuusaku is The Man! I swapped out my 100M osc for a 25M osc and my NES clocking is now much more accurate!! With 100M the best I could get was: DCM Output = 44MHz 2A03 = 44M / 24 = 1.83 MHz (~2.23% faster than original NES) 2C02 = 44M / 8 = 5.50 MHz (~2.23% faster than original NES)...

In this particular case I didn't know if I should assume it was completely wrong since there isn't even a mention of it in your doc or the Wiki at all. In other words, there was nothing to "conflict" with the statement so that doesn't necessarily mean it is wrong. But apparently it is! LOL...

Ok, so I went back and looked in the datasheet for the V5 to be sure I had the correct min input freq. The min I specified is correct. I also ran the architecture clocking wizard to see if it would let me specify anything less than 32 - it would not. !HOWEVER! In looking at the extremely fine print ...

So I tested with Blargg's apps that tepples pointed me to. Only one of them worked. And that was the one that didn't do overlapping $4011 writes and sample reads. Haha. So after fixing my DMC to work like scenario (A) all of Blargg's test apps work now! I'm *VERY* excited! :-D Thanks everyone for yo...

Virtex-5 LXT

2 onboard oscillators available: 100MHz and 25MHz

There is also 1 open oscillator socket (which is what I wanted to put the 21.47727MHz oscillator in).

I found this in BT's nessound.txt: After resetting the 2A03, the first time any sound channel(s) length counter contains a non-zero value (channel is enabled), there will be a 2048 CPU clock cycle delay before any of the sound hardware is clocked. After the 2K clock cycles go by, the NES sound hardw...

I really don't see what it has to do with code portability, for each board you target, you still need to specify hardware constraints There is some truth in that. I suppose requiring the user to figure out how they want to generate the input clock to the system is not really asking that much. Haha....

It's not that simple. In Xilinx devices the DCMs (what you're calling a DLL) and PLLs are restricted to certain minimum/maximum input/output clock frequencies. You are also restricted to certain M / N values based on those frequencies. In my case with my particular boards it is not possible to achie...

Are there any vendors that you can buy a 21.47727MHz oscillator from? I can find some vendors that have 21.47727MHz *crystals*...but no oscillators. And I don't want to have to make an RC-network in order to get an oscillator unless I absolutely have to. :( Anyone know where I can buy one (or a few)...

Growing up my friends and I always called it "N" "E" "S" or just straight "Nintendo". I never even knew people called it "Ness" - that's really interesting and funny (at least to me). LOL Reminds me of the Lochness monster - Nessie. :-P Super Nintend...

This is all pretty interesting stuff. Is there any particular format that lends itself better to being able to to insert little title screens in between captures? Can someone suggest a software package? For example, I want to record the output (audio and video) from my NES-FPGA using my frame grabbe...