nesdev.org

It's one deletion, not three. This can be seen in the signature bits row in the Eighty demo. OK, I stand corrected. I wonder however, would only one joystick button deletion (DMC DMA coincidence) happen on a Nintendo machine like this? (is this even an official Famicom schematic?) I guess I would j...

Could someone explain such behaviour of $4016 and DMCs, regarding an extra read? In the case that a DMC DMA cycle falls on a 6502 bus read cycle (say a read from $4016/7), the processor will be stalled for 3 bus cycles (so here, $4016 will be read 3 times with the bus data thrown away), then on the...

tepples wrote:Unless you want to emulate a room full of NES consoles or an arcade full of Vs. or PC10 machines.

I wonder what sort of video hardware you would need on a PC to output so many display signals, because then speeding up emulation would be very practical (it beats having 1 PC per NES console).

I welcome the day when simulators will be able to run full-blown digital representations of decapped chips like the 2A03 & 2C02, so that us programmers will no longer require knowledge of how the chip works to get a retro system to work properly (for just the simple purpose of entertainment and ...

I privately wrote a working, pure real-mode x86 ASM-coded (source: 4600 lines; code/data size: 11KB), DOS-compatible (works under Win98 too) emulator with about 10 mappers of support, full 2A03 sound channel implementation w/SB16-only stereo audio playback, a keyboard-button game-jump multitasking f...

In addition to discussing the paradigm behind the PPU's Sprite 0 hit depending on the playfield pixels being solid, some attention has to be paid to the 2A03 audio hardware, most notably the sweep units. If you look at the size of the silicon real-estate that the 2A03 consumes for it's audio unit co...

Makes you wonder why Nintendo went with the whole sprite/background collision and didn't just trigger the flag when the first non transparent pixel of sprite 0 was drawn instead. There really is no reason to have it only happen when the background and sprite are non transparent unless the hardware ...

Since those sprites are transparent and have priority over all others, no sprites will be visible up there. The sprite overflow flag, which will be set at the same time every frame, is used for detecting the end of VBlank, so that I can wait for the end of the blanked area and enable background ren...

I don't think the Sprite Overflow flag is ever intended to be relied on and I don't think any commercial games used it for anything. Atleast, I don't remember ever implementing that flag in atleast one of my NES emulators and it never seemed to cause any problems. But it's been awhile. Well I guess...

For a stable horizontal playfield split, use Sprite 0 hit (possibly combined with DMC IRQ). You can shuffle the rest of the sprites fine. Well, I know I can use Sprite 0 hit to do that, but the basis of this query is to establish some community consensus for the fact that the Sprite Overflow flag i...

TL;DR Just cycle sprites all the time if you're creating a game where sprites may (or may not) be in the same scanline at the same time. I was thinking more along the lines of using the flag for a stable, horizontal playfield split, but that's not going to be possible when I've gotta rearrange OAM ...

So... the sprite overflow flag doesn't necessarily get set when there are more than 8 sprites on one line, because as has been documented on the Wiki, once 8 sprites are found, the PPU starts interpreting tile index, attribute, and X coord data in sequence as Y coords for every 3/4 sprite records in...

Hi, As many have said before, by 1987 semiconductor ROM sizes were as large as 128KB, and that was the equivelant to both sides of an FDS disk image. This has been the suggested reason as to why the FDS was dropped from Nintendo's product line, despite having its own awesome extra sound channel gene...

Ah, I see. Thanks for the clarification on Battletoads use of direct PCM writing (no wonder those samples sounded pretty good!). Reading the controllers twice is a pretty nice idea to avoid the DMA bug; I can see now that this wouldn't be the most obvious thing for coders to do, while trying to prog...

Hi, According to the wiki, DMC DMA cycles are suggested to be 4 CPU clocks long (or less), with the first 3 clocks being just re-reads of the presently executing CPU clock (due to possible interrupt stack writing behavior which cannot be stopped on the 2A03's 6502), and then the last clock being the...