nesdev.org

Second level in Battletoads is a bitch. If it's any help, a hang means your CPU is too fast relative your PPU and enables rendering too early (before the vertical bump on that scanline, meaning the vertical bump occurs). Battletoads is only really sensitive in one direction, and having the CPU be re...

It uses blargg's blip_buf by the way, and syncs audio to video by adjusting the pitch slightly to maintain a preset audio buffer fill level. The parameters for the latter are hardcoded at the moment, and the approach probably isn't optimal. Should try James' approach.

In case anyone's interested, I've put a WIP of the emulator I'm working on on GitHub: https://github.com/ulfalizer/nesalizer.

Currently Linux-only and lacks a GUI and save states, so not really worth using yet, but I might get some testing out of it at least if I'm lucky.

In case it's helpful to future people pulling their hair out over this one: To pass, it's important that the first $4014 write lands on an even cycle (and so only adds a single dummy cycle). Since the test synchronizes to the DMC, getting this right depends on the DMC clocks happening on even cycles...

Yeah, agreed-upon names would've been nice. I have a mix of them from different sources in my implementation. :| TIck-by-tick execution is determined by the addressing mode for the unofficial instructions as well, so nothing complicated there. Some instructions have bus conflicts though: http://foru...

If you're counting in half-cycles, φ1 would be even half-cycles and φ2 odd half-cycles. That seems like a weird way to think about it though. φ1 is just the first part of the CPU cycle and φ2 the second.

http://wiki.nesdev.com/w/index.php/CPU_pin_out_and_signal_description was updated recently and covers it too. If you're referring to my recent 2 updates: those were in response to the bottom half of this blog post (FYI: Japanese, and Google Translate is not sufficient here). Basically the post cons...

Why are the instruction lengths for JSR and JMP Absolute set to 4 in that table by the way?

If an emulator encounters an unofficial instruction it's likely that it's either executing bad code or that the instruction is crucial for the code to work though, so not sure how helpful it would be to just skip over it. I was under the impression that the use case was procrastination . Unofficial...

I've seen GCC generate that lookup-table-in-integer approach for some switches. It's pretty neat. If an emulator encounters an unofficial instruction it's likely that it's either executing bad code or that the instruction is crucial for the code to work though, so not sure how helpful it would be to...

Each cycle has a φ1 and a φ2, of equal length. The φ1 half-cycle occurs while the input clock is low, the φ2 half-cycle while it is high. They do not span a full cycle, if that's where you got even/odd from. http://wiki.nesdev.com/w/index.php/CPU_pin_out_and_signal_description was updated recently a...

Started digging into the circuitry a bit, and it looks like the 2A03 handles rdy for OAM DMA and PCM reads in a pretty clever way. Rather than just pulling rdy low for a fixed safe "minimum" time, it first pulls it low and then waits for a CPU read. Once it sees a read, it knows rdy must h...

A test for that would be nice if you ever update the apu_test tests. I pass all of them without implementing it.

Ahh, that explains it. Hadn't realized silence on the DPCM channel worked like that. :mrgreen: So the bits remaining count is updated each DMC clock regardless of whether a sample is playing or not, and the DPCM can only transition from silent to playing at the boundary after a "silent sample b...

But wouldn't the coarse loop in end_dmc_timer always iterate between (428*7)/16 = 187.25 and (428*8)/16 = 214 times, regardless of timing? end_dmc_timer starts a new sample, and that should set the number of remaining bits to 8, meaning it'll have to go through 8 DMC clocks before loading the final ...