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There is something I don't get in end_dmc_timer , which might also be a clue to what's wrong with my code/understanding. The coarse sync part looks as follows: ; Returns in XA number of cycles elapsed since call to ; time_code_begin, MOD dmc_timer_modulo. Unreliable if ; result is dmc_timer_max or g...

3gengames wrote:Isn't it consecutive writes the first one is the only one that takes effect? At least that's what I thought was determined from all tests, ever.

Yeah, that was what I meant - "...all writes but the first always being ignored..."

Thanks for the investigation. Another thing I'm curious about is the precise circumstances where MMC1 ignores writes. thefox implied it's not as simple as all writes but the first always being ignored for consecutive writes (can't remember where he said that though). Emulating it like that fixes Bil...

blargg wrote:I added more comments in sync_dmc.s and dmc_timer.s: sprdma_and_dmc_dma2.zip

Thanks.

Was occupied for a while, but I'll start looking into it now.

Yup, got that much. Trying to understand how the test code itself works and what assumptions it makes though since the output is so off despite passing all the APU tests.

Still a bit confused as to what this test is doing and expects to happen at different points. For example, the test_ routine which gets called 10 times to test different sample loading locations starts like test_: jsr print_a pha eor #$FF pha setb $4012,<((dmc_sample-$C000)/$40) jsr pre_test jsr tim...

blargg wrote:Full sources + rom: sprdma_and_dmc_dma.zip

Thanks!

Haven't traced through the code to figure out what's going on yet, but for some reason the output ends up way off. I pass all the apu_test, apu_reset, and cpu_interrupts_v2 tests (and all the ppu_vbl_nmi tests except 07-nmi_on_timing.nes (off by 1-2 ticks - might be some analog thing going on there)...

blargg wrote:Looks like it was an off-the-cuff test. I've located the source and will package it the next time I'm on my old Mac.

Would be appreciated. Could PM it too if you have it and feel like it - off-the-cuff state if better than nothing.

Is source code available for the sprdma_and_dmc_dma test roms?

I know very little about these sorts of analog effects, but since Visual 6502 seems to get the SAX right I expected it would get ANC/ALR/ARR right as well. For a high-level overview, it has to do with a line being driven to 0 and 1 simultaneously (i.e., having power applied to it and also being sun...

For what it's worth, I set the status flags based on the & result for those instructions and pass blargg's instr_test-v4. Haven't looked at how comprehensively it tests those instructions though, but it seems to be a more comprehensive test than nestest overall at least.

Here's my setup, which works for Punch-Out!! at least (not sure if it's accurate in all situations when different kinds of magic tiles appear next to each other): I have two booleans low_bank_uses_0FDx_reg and high_bank_uses_1FDx_reg . I keep track of the previous value on the PPU's address bus each...

Do you update the mappings when $Bxxx/Cxxx/Dxxx/Exxx are written to? Remember that the magic tiles only select which registers select the low/high CHR page. Writing those registers will also update the mapping.

Found something familiar in the Journey to Silius soundtrack:

http://www.youtube.com/watch?v=dNCrpIL2XlY&t=11m37s vs. http://www.youtube.com/watch?v=pFZZ3o7lXvo

Close enough that the first one immediately made me think of the second at least.