nesdev.org

Alright
I have debugged megaman 2 and found u said

but what is the other way to scroll with only 1 nametable ?

I was trying in megaman game

I used an open source emulator to view the name tables but what I found that 2 name tables are similar ( due to mirroring ) and the other two are black ( I expected to see the next screen in them )

ok this is good,
So why i didn't see this in emulator ppu debugger?

Hello NES dev :D I have a question about scrolling I understood how the loopy_v and loopy_t makes scrolling possible, my question is from programmer point of view as I understood, I f i will use vertical mirroring , I put the name table data in " a " name table and the hidden screen in the...

On a real PPU, it locks itself for a frame or two. You can't enable rendering until it has 'warmed up' over two vblanks worth of time. what do you mean exactly by " it locks itself " and " warmed up " ? another question , what about the emulation ? does it also the same as the r...

Hello NES DEV :D I have a question related to this timing diagram http://wiki.nesdev.com/w/images/d/d1/Ntsc_timing.png I now understand it for except a small thing , what happens when the ppu starts up ( or resets ) ? i think it starts at scanline 0 but this will make the first 2 tiles , sprites on ...

So , as I understood from the code , when I request a read from VRAM , what I really get on the data bus is the previous read read #1 read #2 read #3 as I understood , what I get in read#2 is the result from read#1 and in read#3 is the read#2 so generally, the read to 2007 transfers the content of t...

That's correct. I don't know much about the timing, just that there's a delay when reading, because there's not enough time for the PPU to fetch a byte from VRAM and return it to the CPU during the load instruction that triggered the read. For this reason, the byte fetched from VRAM is buffeted, an...

So, what I understood ( and tell me if I am wrong ) the read/write signal to 2007 determines if I will write to VRAM or not if read from 2007 then the PPU will read the VRAM of address in 2006 if write to 2007 then the PPU will take the data in 2007 and write to VRAM of address in 2006 but , what ab...

It's pin 1 (R/W), apparently:

but I think those for reading/ writing to PPU internal registers

the CPU will output a signal indicating whether it's reading or writing data. This signal is essential even for memory to work correctly, because memory chips need to know whether they're being written to or read from. Anyway, the PPU too can see this signal, so it knows whether to read from our wr...

I will illustrate my question with example we know that the CPU can't access the VRAM directly, so we need to first to write in 2006 and 2007 ( if writing ) I am not familiar with NES assembly but i will try. assume i will write FF to the VRAM in address 0x1000 LDA 00 ; load accumulator STA 2006 ; 1...

OK I understood this all , but I think I haven't explained it well my question is how to tell the PPU to write to ( or read from ) the VRAM for both reading and writing , both registers are used , so I think there must be an input signal according it the PPU will know if the data in the registers is...

VRAM is accessed exculively with $2006 and $2007 I have a question here, I searched in the PPU registers documentaion about how the PPU differentiate between the read to VRAM and the write to it through both registers , but I found nothing There is a read/write pin for the 2A03->PPU communication, ...

VRAM is accessed exculively with $2006 and $2007

I have a question here, I searched in the PPU registers documentaion about how the PPU differentiate between the read to VRAM and the write to it through both registers , but I found nothing