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The 6280 is probably using a rather skewed duty cycle for access then, or they went with overlapping phases and hoped for the best. As for the SA-1, the rom there was 90-100ns, 10.7MHz access cycle, or 2 master clocks. The 5A22 gets two cycles for one access, the SA-1 then gets two cycles for two ac...

Haven't seen timing diagrams for the 6280, but I'm betting the address bus didn't quite work like that. Clock speed isn't really the right term for these memories anyways, since they're all async. It's more likely it still had the 2x requirement, and used the off-duty half of the CPU cycle for refre...

That would be due to how the clocking works on the 6502 and 65816. The input clock is turned into two mutually exclusive clocks, phi1 and phi2. phi1 controls the address bus and data out latches, instruction register, and most of the internal control signals, including the various register loads. ph...

If your APU isn't running on a per cycle basis, how could it possibly be doing the DMA cycle stealing correctly?

The TG16 ran at 7MHz, and packed all sorts of instructions that should have been on the 6502 to begin with, and had some block move instructions to cover for DMA. Only the PRG made it to the cart there IIRC, and it was a vram based console more like the snes, though with fewer colors, only one BG la...

That probably just means that the games don't rely on the different behavior.

Fascinating stuff. This suggests a shared DMA unit, running on a 2-cycle period, writes happening in the first period, reads happening in the last. There's probably a start flag that suppresses the address bus switchover for the first 1.5 cycles. Random brainfart guess as to what the sequence and pr...

$21xx hits everything on the B bus, which includes the PPU, WRAM, expansion, and cart edge. The A bus hits the cart edge and S-APU. WRAM has two sets of pins on it, one for talking to it via the A bus, and others for talking to it via the B bus at $80..$83 with the streaming reads/writes. If both ar...

A full PPU bus would have meant another 50 or so pins on the cart connector, and at least 3 more chips, since the PPU has two mostly independent memory busses.

If they were ever considering a switched rom, they would have had to toss mode-7.

There is not, and can not be.

I think you have a CPU bug to deal with. It looks like there's a JSR at E176, which pushes E178 onto the stack at 1FE and 1FD around cycle 937 This subroutine appears to have a PHsomething at E126, which pushes 02 into 1FC The IRQ fires at 1257, during an instruction at E138, which gets pushed into ...

i_cpu_do is probably data out from the CPU, so won't match the opcodes. I think.

What game is poking at the PPU nametable mirrors?

As for the CPU glitches, blargg's cpu exerciser tests can be somewhat handy, if a bit unwieldy for determining what's actually going wrong. I think there's still a link to the suite somewhere. I used them to get some sanity checks on my verilog core, which I think is mostly bug-free now (for the doc...

pinout suggests it was getting the 1.789MHz clock, however, the counter could have just been clocked directly by A12. Do your checks at 21MHz, with some sort of lowpass on the thing as mentioned. Going by the wiki claim of it ignoring edges less than 14-16 dots apart, something like this might do it...