Search found 9 matches

by jwiggams
Wed Aug 05, 2020 1:23 pm
Forum: SNESdev
Topic: SNES mapper testing
Replies: 4
Views: 3540

Re: SNES mapper testing

Address bus is stable, /WR or /RD falls, data bus must be valid by rising edge. Got it! I had thought that nCS was needed because it's low when accessing the ROM space and as such would be high whenever I was accessing the $2200-3FFF range, but I've since changed my code to clock on the rising edge...
by jwiggams
Wed Aug 05, 2020 12:16 pm
Forum: SNESdev
Topic: SNES mapper testing
Replies: 4
Views: 3540

Re: SNES mapper testing

"nCS" is not an edge in the SNES. You have to clock your behavior, if you're using edge logic, on /RD or /WR (or PAWR or PARD) as appropriate. (nCS in the SNES is literally just a function of the address bus, lines A23-A17 and A15) So what would it look like if accessing that region? Shou...
by jwiggams
Wed Aug 05, 2020 11:44 am
Forum: SNESdev
Topic: SNES mapper testing
Replies: 4
Views: 3540

SNES mapper testing

I'm working on a custom mapper project for SNES electronics project to control some LEDs, using $2200-3FFF range. I've got a test ROM that you can put an address in, and write a byte value to that address. When I do this, things mostly don't work (LEDs either don't come on or have wrong state) - mea...
by jwiggams
Mon May 18, 2020 12:27 pm
Forum: NES Hardware and Flash Equipment
Topic: Trouble with level translation and wram
Replies: 2
Views: 1989

Re: Trouble with level translation and wram

Ahh of course! I knew it was something simple. I wasn't taking into account that "console_prgce && console_prgrw" would be a logic 1 when the console is trying to read from wram, as both of those pins would be high during reads. Makes sense that it wasn't working now. Thanks for th...
by jwiggams
Mon May 18, 2020 11:21 am
Forum: NES Hardware and Flash Equipment
Topic: Trouble with level translation and wram
Replies: 2
Views: 1989

Trouble with level translation and wram

I'm making a simple adapter that sits between the NES console and the cartridge, and for the most part it works but not with games that use WRAM. All signals pass through an FPGA which is connected serially to my pc, so that I can sniff around while things are running. Most games work fine, but anyt...
by jwiggams
Tue Feb 21, 2017 12:16 pm
Forum: SNESdev
Topic: Byteswapping SNES on purpose
Replies: 12
Views: 4481

Re: Byteswapping SNES on purpose

Thank you everyone for the feedback.

I'll leave the idea alone for this right now. Doesn't seem worth the hassle at all, especially for the extra difficulty and cost involved.

Thanks again
by jwiggams
Mon Feb 20, 2017 6:56 pm
Forum: SNESdev
Topic: Byteswapping SNES on purpose
Replies: 12
Views: 4481

Re: Byteswapping SNES on purpose

Tepples meant to say "an inverter". So would something like one gate on a 7400 work? With inputs connecting to SNES A0 and the output going to ROM A0? However, as is always the case with DRM schemes (and this is one), it really just comes down to the question of: how much effort you want ...
by jwiggams
Mon Feb 20, 2017 2:15 pm
Forum: SNESdev
Topic: Byteswapping SNES on purpose
Replies: 12
Views: 4481

Re: Byteswapping SNES on purpose

Thanks for the reply!

I guess I didn't think of those dumpers... I may have to think of other options.

But as for the using a XOR between A0 on the cart bus and A0 on the ROM, how does that do the byteswapping? I thought that was all controlled by the data pins?
by jwiggams
Mon Feb 20, 2017 12:52 pm
Forum: SNESdev
Topic: Byteswapping SNES on purpose
Replies: 12
Views: 4481

Byteswapping SNES on purpose

Hey all, new here but figured this was a good place to ask: I'm working on a demo for SNES, and I've been looking into building a custom board for it that uses byteswapping as a cheap and easy (albeit not super effective, I know) method of anti piracy. It's more of a deterrent than actual protection...