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Because some instruction have an Internal Operation cycle whilst RWB is '1', so CPU_RD would go low even if no read cycle is executing. To determine Internal Operation cycle I use VDA and VPA, maybe it wrong. Non you are not wrong,, VDA and VPA are useful to determine IO cycle, but then, /CPU_RD wo...

tDECOD is combinational propagation delay to decode CPU_RD from full address (bank + offset) and RWB signal. Why do you think that CPU_RD is decoded from address and not just RWB? I think it something like ~(RWB & PHI2). Because some instruction have an Internal Operation cycle whilst RWB is '1...

According to the logical analyzer traces from this post (LISTING8.txt) CPU_RD/CPU_WR is 3/3 and 3/5 master cycles long when work CPU and 4/4 when work DMA. Yes, but I can't tell why the differences between those logs and my timing diagram. Maybe bank latching is not done in SNES as explained in W65...

Hope this handmade timing diagram will help to explain why I don't think CPU_RD is 3 master cycles in FastROM mode: STA_4801.jpg There are 2 more CPU cycles left, but to illustrate how it works, it is sufficient. tLATCH is latch's propagation delay from enable = '1' to output valid. tDECOD is combin...

Thanks magno, you are the only one who gives very useful information. I have little experience in this. Thanks to you! It is really nice to have such technical conversation with people who know what they are talking about. I read all this information in the W65C816S datasheet from Western Digital (...

Can so you will understand that I mean Документ1.png I understand what you say, but that timing diagram is not correct. Address bank appears on data bus at most 33ns after PHI2 falling edge (your signals are rising-edge-aligned, but I think the correct is falling-edge as in PHI2). This byte is latc...

Thus, one CPU cycle is one ROM reading for SDD1. Nop, a CPU cycle is 6 master clocks in FastROM, or 8 master clocks in SlowROM (not the case). The read cycle is just a portion of 1 CPU cycle. After writing to $4801 and before starting DMA are 9-10 CPU cycles. I use first 6 for loading compressed da...

xxxmap.vhdl files implement cartridge interface. Ahh, ok, ok. You see? I missed something! :mrgreen: In the first files you shared, there wasn't any interface for controlling ROM or SRAM, so that implementation could never work, whatever the implementation of the SNES (real hardware or FPGA). I see...

Or did you implement full SNES in an FPGA? That would be great then! Yes. Great!! It would be nice there were some open-sorce projects for SNES FPGA implementation. It could be use for homebrew, getting the most of SNES system, adding features... Of course SRAM is present, 8 Mbyte split by 6 Mbyte ...

I run its on my FPGA SNES, my board with LCD 5" 800x480 RGB. I've never seen a real console :( . Oh, do you mean SuperNT maybe? Or did you implement full SNES in an FPGA? That would be great then! For ROM I use two SRAM 4Mx8 55ns, therefore it works on 2 cycles. But you don't enable the ROM fr...

So, with magno’s help I finally launched SDD1 on FPGA SNES. Not sure what will work on real hardware. Also not tested in 8BPP modes. So far I have achieved 3 master cycles for ROM access. Also I don't know how SDD1 should work if more than one DMA channel is selected for it (header is common or dif...

Smaller. The neviksti hack is 12 MB, so I assumed that was the uncompressed size of the game. Neviksti's version is 12MByte but must of the ROM space is not filled with data. He left untouched the first 48Mbit (the original ROM) then used 3 bank to make a big lookup table for pairing each compresse...

65.5 megabits sounds close to 64*1000*1024 bits In fact, my Star Ocean version is 65.5 * 1024 * 1024 bits. It spans 132 LoROM banks (32768 bytes each) and 64 HiROM banks (65536 bytes each). And I too am curious about typical compression rates over the S-DD1 corpus. If you have time, it'd be interes...

I myself did it for Star Ocean too, resulting in a 65.5 Megabit ROM. ...wait, what? Is 65.5 Megabit bigger or smaller than you expected? What kind of average compression ratio do you see with graphics? I could make calculations about it if you are interested. Most of the SDD-1 chunks are 8x16 4BPP ...

A thing that I've found interesting is that there's an early prototype that didn't use the SDD1. Seems to be an early version, but maybe the chip can be just left out by using a larger ROM. Yes, that can be done; Nevitski did for Star Ocean and I myself did it for Star Ocean too, resulting in a 65....