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Since I have the GSU-1 and GSU-2's complete pin-out, I decided to update the Eagle library adding the SuperFX. I have the proper package width and height measured directly on the PCB, but I find hard to get the exact pin distance... Anyone knows? Maybe it is an standard TQFP112?

If you want 100% accuracy then ditch the emulator and use real hardware. Sorry, but I have learned that emulators shouldn't be trusted at all - even when they emulate things like cycle-level operations and such, they still won't emulate issues like the hardware crashing if you try to access it too ...

From the romhacker point of view, I really prefer the header not to be supported and I really don't care about ZIP support. Why? 1) When reverse-engineering the code in a ROM, I prefer the ASM code to be referred to address $0 in the file, not $200 or whatever: easy to make calculations without calc...

Sure, I'd be glad to take a look, and probably add some of the new chips. I definitely won't be keeping the pin number silkscreen changes though. I un-did the changes on this because it caused troubles with iTEADStudio DRU rules. I reverted the "gold finger" pin numbers to your originals....

I have a board outline for the carts with expansion wings as well, trimmed a bit to fit within the 10cm width (the original carts are 102mm, not a huge deal, the fitting slots are still there). I have outlines for the No-RAM boards, the normal-sized boards without wings, and the full-sized boards w...

lidnariq wrote:It is a BJT, specifically the 2SD2145. And it's NPN.

Really?! You made my day!! Thank you very much for the information!

I checked 2SD2145 datasheet and couldn't figure out if it is PNP or NPN, but anyway I trust you. I think the circuit I posted above makes sense now!

Hi guys, I'm trying to make schematics from all SNES cartridges I have and I started by the "easiest": Super Mario World. The board is labeled as SHVC-1A1B-06, with SRAM but no MAD-1. In this board, SRAM is powered by a diode during stand-by, and its /CS is driven by some weird device labe...

Thanks for the replies.

I think I'll try WLA_DX because it keeps the same syntax for ASM instructions and some directives are common.

Hi there! I'm coding a lot of routines for Romancing Saga 3 translation to Spanish (please check Traducciones Magno ). Everything was ok until 2 hours ago, when I realized I can't compile my source code anymore using "x816" assembler... Why? Because my source code is really big now (all .a...

Oh I see, well I think the data bus is Hi-Z from a few ns after Phi1 until 30ns after (/CE OR /RD) == 0. From that moment until /CE is asserted for 120ns there is invalid data on the bus, but there's still something. Maybe the data is present but invalid, I don't know... but I prefer to simulate it...

Phi1 is the same as Phi2, inverted, so by it I mean the low period of Phi2. Ok, thanks :D Still in your diagram I think ROM data should be valid earlier. The /OE delay on a 120ns ROM I believe is 30ns max. I didn't take that into account because /RD is asserted far before that data is accessed on M...

I guess I'm not being clear, /RD and /WR are valid AFTER Phi2 is high (/RD = Phi2 NAND RWB), /RD and /WR must follow Phi2 (like the 6502) or memory couldn't be latched with /WR and /RD would conflict with the bank register. Right! I forgot to add that condition :D Also I think the address is valid ...

Well, this is the result of my simulation; I assume 25 ns of delay on decoding each signal and 25 ns too on latch's propagation time. http://img33.imageshack.us/img33/791/snesreadcycle.png As you can see, in FastROM read cycle, the maximum ROM time access is 124 ns. I assume /RD and /WR are decoded ...

GREAT! Phi2 is the CPU clock, isn't it? So it can be 3.58MHz or 2.86MHz... I'm doing a simulation with Modelsim to add all those signals plus the 65C816's outputs. EDIT 1: Acording to 65C816 datasheet, RWB is asserted at the same time that A0..A15, so your signal R / /W should be aligned in time wit...

The reason the first way didn't work is because you are enabling the 257 with /RD. /RD is asserted on every memory read so you are trashing the bus. In the other thread I used a 139 decoder to create an OR gate (/ROMSEL OR /RD) which is the proper condition. I think you could change around the MAD-...