Search found 193 matches
- Sat Feb 05, 2011 8:21 am
- Forum: SNESdev
- Topic: SNES ROM access timing
- Replies: 40
- Views: 16647
I believe the reason exchanging the signals still worked is because the 816 doesn't have picky timing. On another CPU, such as one with many cycles per fetch, /RD might only assert on the last state/phase of a cycle and asynchronously enabling the ROM any earlier could cause a bus conflict with int...
- Fri Feb 04, 2011 2:33 pm
- Forum: SNESdev
- Topic: SNES ROM access timing
- Replies: 40
- Views: 16647
I understand how you think it should be but did you verify that your /OE pin is really /OE? Do you have the timings now? No, I didn't verify it, I assumed what I found in ROMLab as true... But now I realize you're right, becasue it makes sense: /ROMSEL enables the MaskROM only when it is needed, th...
- Fri Feb 04, 2011 4:40 am
- Forum: SNESdev
- Topic: SNES ROM access timing
- Replies: 40
- Views: 16647
I understand, but where did you get your mask ROM pinout? This is the only discrepancy. I can't read the diagram clearly but what looks like /OE is connected to the MAD-1 and /CE to /RD, backwards. I got the pinout here: http://nintendoallstars.w.interia.pl/romlab/snesroms.htm And yes, MaskROM's /O...
- Fri Feb 04, 2011 2:39 am
- Forum: SNESdev
- Topic: SNES ROM access timing
- Replies: 40
- Views: 16647
Of course your understanding of /RD (/OE) and /ROMSEL (/CE) is correct, but it conflicts with what you posted earlier and with the cartridge diagram. The cartridge diagram is not a repro... it's actually what is routed on the PCB that host an original Chrono Trigger (Japanese). I mean that I repres...
- Fri Feb 04, 2011 12:30 am
- Forum: SNESdev
- Topic: SNES ROM access timing
- Replies: 40
- Views: 16647
English is my first language and yes I thought he was being a dick . The OP starts with a somewhat arrogant tone (probably I'm the only one to see because I posted diagrams, including a 257 one, in the thread referenced), then I was replied to with ellipsis, bolded keywords and datasheet parameters...
- Thu Feb 03, 2011 1:55 pm
- Forum: SNESdev
- Topic: SNES ROM access timing
- Replies: 40
- Views: 16647
That's NOT like it sounded... but anyway, I didn't feel offended and I'd rather read somebody's explanation to my doubt than those kind of comments.MottZilla wrote:He wasn't insulting you. He was giving you a recommendation and saying he's not trying to "be a dick" to you.
Anybody knows the answer?
- Thu Feb 03, 2011 2:21 am
- Forum: SNESdev
- Topic: SNES ROM access timing
- Replies: 40
- Views: 16647
(and not be a dick). Why are you insulting me? You could correct me if I'm wrong, instead... Just like I did with you, because MaskROMs used with a decoder AREN'T -100 ns speed grade, I checked it... And I also checked that -120ns EPROMs work with some games and not with others... And I prove what ...
- Thu Feb 03, 2011 1:18 am
- Forum: SNESdev
- Topic: SNES ROM access timing
- Replies: 40
- Views: 16647
That would make the mask ROMs used with an address decoder actually 100ns. Umm... don't think so... The MaskROM is usually enabled by /RD , which I think it's not decoded from the address bus, but it is a signal from the 65C816. That means MaskROMs are enabled just when the address appears on the b...
- Tue Feb 01, 2011 11:41 pm
- Forum: SNESdev
- Topic: SNES ROM access timing
- Replies: 40
- Views: 16647
Because the original 65816 is pin compatible with the 6502 - it takes advantage of the two phase bus access system of the original 6502. In order to get the full 24bit address on a 16 pins, the data bus is used to hold the upper 8bits. This is attached to an external latch. The phase switch from 1 ...
- Tue Feb 01, 2011 2:46 pm
- Forum: SNESdev
- Topic: SNES ROM access timing
- Replies: 40
- Views: 16647
Also, I don't see why the block transfer instructions would make any difference. Even if it was 6 cycles master cycles a byte, 120ns is within range of that. 3.579545mhz is 279ns. And given the multiplexed bus and the requirement for the data bus to be valid in half that time, that's 139ns. So 120n...
- Tue Feb 01, 2011 7:04 am
- Forum: SNESdev
- Topic: SNES ROM access timing
- Replies: 40
- Views: 16647
Re: SNES ROM access timing
My Apple IIGS book says MVN and MVP take 6 CPU cycles, which is a lot longer than 6 master clocks. (Each CPU cycle is usually 6 or 8 master clocks.) From http://wiki.superfamicom.org : A CPU internal operation (an IO cycle) takes 6 master cycles. A memory access cycle takes 6, 8, or 12 master cycle...
- Tue Feb 01, 2011 12:16 am
- Forum: SNESdev
- Topic: SNES ROM access timing
- Replies: 40
- Views: 16647
SNES ROM access timing
Hi everybody, I'm doing a repro of Chrono Trigger using 27C322. I've read the thread about this and analyzed the scematics, but I prefer my solution of using 74HC257 muxers to convert the EPROM's 16bit data-bus to the SNES' 8 bit data-bus. Anyway, my questions are related to timing: * which input-to...
- Fri Jan 14, 2011 2:03 pm
- Forum: SNESdev
- Topic: BSNES debugger
- Replies: 25
- Views: 15914
- Fri Jan 14, 2011 2:43 am
- Forum: SNESdev
- Topic: BSNES debugger
- Replies: 25
- Views: 15914
- Tue Jan 11, 2011 1:14 am
- Forum: SNESdev
- Topic: BSNES debugger
- Replies: 25
- Views: 15914