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Or did you implement full SNES in an FPGA? That would be great then! Yes. But you don't enable the ROM from your SDD1 implementation, there is no ROM_CS nor ROM_OE, which are necessary even if you use SRAM as ROM... And anyway, you need SRAM for Star Ocean. Some variables used by the audio engine a...

don't know if your implementation will work on hardware, so... which hardware did you run SFA2 and SO? I run its on my FPGA SNES, my board with LCD 5" 800x480 RGB. I've never seen a real console :( As for ROM access, 3 master cycles is the miminum for FastROM, since that means 139ns time acces...

So, with magno’s help I finally launched SDD1 on FPGA SNES. Not sure what will work on real hardware. Also not tested in 8BPP modes. So far I have achieved 3 master cycles for ROM access. Also I don't know how SDD1 should work if more than one DMA channel is selected for it (header is common or diff...

magno wrote: I myself did it for Star Ocean too

Star Ocean has 8bpp modes data?

what will happen if 43x2-43x4 is writed after writing 4801 you shouldn't do that, in fact, neither SO nor SFA2 do that. But if you did, S-DD1 would start decoding from the last source address it had sniffed from SNES dara bus, I guess. selected more than one channel SDD1 that's not a problem, you s...

(plus 5 cycles for fist 2 bitplanes for read header and initialize decoder). That sounds fast! Do you use input FIFO for decoding? Andreas Naive wondered if it was necessary, and looks it is for high decodin ratios (up to 128:1). I mean 5 cycles for init decoder and header + 16 cycles for 2 bitplan...

My Decoder takes 16 master cycles for 16 bit of 2 bitplanes (plus 5 cycles for fist 2 bitplanes for read header and initialize decoder). When I created DMA module and SDD1 I was based on this post . I think, decoder should start after write to $420B and fetch next opcode (from line 2490 in post). Bu...

Hi.
I also worked on the SDD1 FGPA implementation for my SNES FPGA. Decoder is working, but embed in SNES yet it does not work.

I'm interested, how many master cycles does it take to decode first two bytes (one row) and the rest in your implementation?

The only mention of the operation of the bus SA1 that I found is "SNES Development manual Book II". Does anyone have any information about SA1, especially about the bus conflict, when SCPU and SA1 both access the same memory? I am interested: in what moment SA1 paused its core relative to ...

So, I asked and I answer. OPT data read from BG3 Map Table, 3 (4 if tile size 16x16) lower bits of scrolling offset not use in this case. Therefore no need in addition lower bits BG1(2)HOFS to BG3 horizontal scrolling offset. I think the formula should be that: HOFS = X + BGnHOFS VOFS = Y + BGnVOFS ...

Maybe I'm stupid, maybe my bad English is the problem. I formulate a question on another.

For example, in Mode 2 enabled BG1 and BG2 with different scroll values and size 64x32. How to calculate the position in BG3 Map memory region to get the horizontal and vertical offsets for BG1 and BG2?

HOFS = X + BGnHOFS VOFS = Y + BGnVOFS ValidBit = 0x2000 for BG1, or 0x4000 for BG2 if (!IsFirst8x8Tile(BGn, HOFS)) { /* Hopefully these calculations are right... */ Hval = GetTile(BG3, (HOFS&7)|(((X-8)&~7)+(BG3HOFS&~7)), BG3VOFS) Vval = GetTile(BG3, (HOFS&7)|(((X-8)&~7)+(BG3HOFS...

0.000004208333333, 0, 0, 1, 0, 1, 0, 0, 1 ; BG2 nametable .1666 us 0.000004375000000, 0, 0, 0, 0, 0, 0, 0, 1 ; BG1 nametable .1666 us 0.000004541666667, 0, 1, 0, 1, 0, 0, 0, 1 ; BG3 OPT .3750 us 0.000004916666667, 1, 0, 0, 0, 0, 0, 0, 1 ; BG2 4bpp .3750 us 0.000005291666667, 1, 0, 1, 0, 1, 0, 0, 1 ...

Thanks, lidnariq's test rom very helped me.

Now I add Offset-per-tile mode in my FPGA SNES, for now I did Offset-per-tile only for BG1 in BGMODE 2 (it works in Tetris Attack, Battletoads in battlemaniacs and SNES burn-in test rom), and I have a few questions. As I understand, scrolling values in BG3 common to BG1 and BG2, but read 2 times: on...