SPC Echo/FIR filter flowchart documentation (is it correct?)

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jimbo1qaz
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SPC Echo/FIR filter flowchart documentation (is it correct?)

Post by jimbo1qaz »

After studying SNES docs, Anomie's docs, and Higan/Game-Music-Emu source code for days, I wrote up a flowchart for the structure of the SNES echo and FIR filter system. Can anyone verify that it's correct? Especially the FIR filter part?

http://bin.smwcentral.net/u/22354/snes-echo2.out.png

Note that _echoPointer, echoOffset, echoHistory, and calculateFir are references to Higan source code. EON is a flag (bits), EFB, EDL, and ESA are mono, and MVOL and EVOL are stereo registers.

EDIT: Note that ECEN flag must be enabled in order to write to the echo buffer.

Source material:

Nintendo docs: http://pikensoft.com/old/docs/Super_Fam ... edi%29.txt
Anomie docs: https://37.muncher.se/bot/apudsp.txt
Higan source: https://gitlab.com/higan/higan

Repost of http://www.smwcentral.net/?p=viewthread&t=83780
Last edited by jimbo1qaz on Mon May 16, 2016 4:26 pm, edited 3 times in total.
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Bregalad
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Re: SPC Echo/FIR filter flowchart documentation (is it corre

Post by Bregalad »

Looks correct to me.
jimbo1qaz
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Re: SPC Echo/FIR filter flowchart documentation (is it corre

Post by jimbo1qaz »

Bregalad wrote:Looks correct to me.
Just to make sure, the FIR buffer is a separate ring buffer in memory, not the echo buffer? Is it a memory region, or stored outside the memory space?
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Bregalad
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Re: SPC Echo/FIR filter flowchart documentation (is it corre

Post by Bregalad »

Well, I do not know whether FIR is implemented with a 8-step shift register, or if each times a sample is produced, 8 samples are read from echo memory. The later solution sounds wasteful, so it's probably the former, but who knowns. This do not makes any difference in functionality, only in circuit design.
tepples
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Re: SPC Echo/FIR filter flowchart documentation (is it corre

Post by tepples »

If they're reread, they can be modified between one read and the next. As for "wasteful", it may be a tradeoff between on-chip memory and main memory bandwidth, both of which cost money. Another example of such a tradeoff is that the NES PPU rereads the attribute byte in the right half of a 16x16 pixel attribute region, which simplifies the logic at the cost of there not being a way for the CPU to access video memory during active picture.
jimbo1qaz
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Re: SPC Echo/FIR filter flowchart documentation (is it corre

Post by jimbo1qaz »

According to Higan, only one echo sample is read every time, and the FIR history is stored in a separate ring buffer array from SPC memory. So that means that the FIR filter history is stored in a hardware shift register, separate from system RAM?
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Bregalad
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Re: SPC Echo/FIR filter flowchart documentation (is it corre

Post by Bregalad »

Yes. But it's not a ring buffer, rather just a 8-sample read-only history of what is read from the echo ring buffer.
If they're reread, they can be modified between one read and the next.
True, but any application which modifies the echo buffer by hand is already testing the edge of the hardware.
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