does SMB use IRQ?

[ember]

hello everyone, i'm making an FPGA-NES emulator and my "step one" goal is to run SMB.
Right now i've almost finish the cpu 6502 and decide to run a part of SMB for testing interrupts and instruments. my issues are below:

a few bytes i focus on in the PRG-ROM like this:

Code: Select all

8000 : 78       sei         ;
8001 : D8       cld         ;
8002 : A9 10        lda #$10        ;
8004 : 8D 00 20     sta $2000       ;PPU 惂屼Reg.#1
8007 : A2 FF        ldx #$FF        ;
8009 : 9A       txs         ;
800A : AD 02 20     lda $2002       ;PPU Status Reg.
800D : 10 FB        bpl $800A       ;
...
...
FFE7 : 18       clc         ;
FFE8 : 16 14        asl $14,x       ;
FFEA : 15 16        ora $16,x       ;
FFEC : 16 17        asl $17,x       ;
FFEE : 17       db  #$17        ;
FFEF : 18       clc         ;
FFF0 : 19 19 1A     ora $1A19,y     ;
FFF3 : 1A       db  #$1A        ;
FFF4 : 1C       db  #$1C        ;
FFF5 : 1D 1D 1E     ora $1E1D,x     ;
FFF8 : 1E       db  #$1E        ;
FFF9 : 1F       db  #$1F        ;
FFFA : 82 80        dw  $8082       ;NMI(VBlank)
FFFC : 00 80        dw  $8000       ;Reset
FFFE : F0 FF        dw  $FFF0       ;IRQ/BRK

The signals showns on SignalTapII seem that the /RST works fine and the PC jumps to $8000 and loops between $800A-$800D because there's no PPU no VBlanks right now. this sequence seems work fine.
but when I try to test IRQ on this, the PC jumps to $FFF0 successfully, then i find the data around $FFF0 doesn't seem like instruments (musics or something else i guess, anyone who knows what's it would you plz tell me something?thx a lot.) and my cpu stoped at $FFF3 because $1A is not a offical opcode. so here come my questions:
1. Do NROM games like SMB NOT use IRQ?
2. when does an IRQ occur in NES subsystem? and what IRQs are used for? are there multiple IRQ sources(APU and mapper?)?
3. What really happens when cpu meets a undocumentd opcode? Is implementing undocumented opcodes necessary? (what i have already done is to let cpu stop and show the PC and opcode on the LEDs on my fpga board.)

thx!

[Dwedit]

SMB1 does not use IRQs at all.
Generally, if the mapper doesn't provide an IRQ source, games won't try to use IRQs. There are a few exceptions though, some games use the built-in IRQ feature of the DMC channel to do split screens, such as Time Lord, Mig 29 Soviet Fighter, and Fire Hawk.
And Chun Soft's really early games (Door Door, Dragon Quest, and Dragon Quest II) use the APU Frame IRQ to drive the music engine of the game.
If the NES hits an undocumented opcode, it tries to execute it anyway. Usually it's a combination of the Read-Modify-Write instruction and the ALU instruction from that row in the instruction table. Look at a table of unofficial opcodes for details.
Very very few NES games use undocumented opcodes. I can only think of Puzznic, Super Cars, and Streemerz (homebrew).

Instruction set summary (with undocumented instructions)

Code: Select all

x                00               01               02               03               04               05               06               07               
                 08               09               0A               0B               0C               0D               0E               0F

00               BRK impl         ORA X,ind        *kil             *slo X,ind       *nop zpg         ORA zpg          ASL zpg          *slo zpg         (SLO is also called ASO)
08               PHP impl         ORA #            ASL A            *aac #           *nop abs         ORA abs          ASL abs          *slo abs
10               BPL rel          ORA ind,Y        *kil             *slo ind,y       *nop zpg,x       ORA zpg,X        ASL zpg,X        *slo zpg,x       
18               CLC impl         ORA abs,Y        *nop             *slo abs,y       *nop abs,x       ORA abs,X        ASL abs,X        *slo abs,x

20               JSR abs          AND X,ind        *kil             *rla X,ind       BIT zpg          AND zpg          ROL zpg          *rla zpg
28               PLP impl         AND #            ROL A            *aac #           BIT abs          AND abs          ROL abs          *rla abs
30               BMI rel          AND ind,Y        *kil             *rla ind,y       *nop zpg,x       AND zpg,X        ROL zpg,X        *rla zpg,x       
38               SEC impl         AND abs,Y        *nop             *rla abs,y       *nop abs,x       AND abs,X        ROL abs,X        *rla abs,x

40               RTI impl         EOR X,ind        *kil             *sre X,ind       *nop zpg         EOR zpg          LSR zpg          *sre zpg         (SRE is also called LSE)
48               PHA impl         EOR #            LSR A            *asr #           JMP abs          EOR abs          LSR abs          *sre abs
50               BVC rel          EOR ind,Y        *kil             *sre ind,y       *nop zpg,x       EOR zpg,X        LSR zpg,X        *sre zpg,x       
58               CLI impl         EOR abs,Y        *nop             *sre abs,y       *nop abs,x       EOR abs,X        LSR abs,X        *sre abs,x

60               RTS impl         ADC X,ind        *kil             *rra X,ind       *nop zpg         ADC zpg          ROR zpg          *rra zpg
68               PLA impl         ADC #            ROR A            *arr #           JMP ind          ADC abs          ROR abs          *rra abs
70               BVS rel          ADC ind,Y        *kil             *rra ind,y       *nop zpg,x       ADC zpg,X        ROR zpg,X        *rra zpg,x       
78               SEI impl         ADC abs,Y        *nop             *rra abs,y       *nop abs,x       ADC abs,X        ROR abs,X        *rra abs,x

80               *nop #           STA X,ind        *nop #           *aax X,ind       STY zpg          STA zpg          STX zpg          *aax zpg
88               DEY impl         *nop zpg,x       TXA impl         *xaa #           STY abs          STA abs          STX abs          *aax abs
90               BCC rel          STA ind,Y        *kil             *axa ind,y       STY zpg,X        STA zpg,X        STX zpg,Y        *aax zpg,x       
98               TYA impl         STA abs,Y        TXS impl         *xas abs,y       *nop abs,x       STA abs,X        *sxa abs,y       *axa abs,x

A0               LDY #            LDA X,ind        LDX #            *lax X,ind       LDY zpg          LDA zpg          LDX zpg          *lax zpg
A8               TAY impl         LDA #            TAX impl         *atx #           LDY abs          LDA abs          LDX abs          *lax abs
B0               BCS rel          LDA ind,Y        *kil             *lax ind,y       LDY zpg,X        LDA zpg,X        LDX zpg,Y        *lax zpg,x       
B8               CLV impl         LDA abs,Y        TSX impl         *lar abs,y       LDY abs,X        LDA abs,X        LDX abs,Y        *lax abs,x

C0               CPY #            CMP X,ind        *nop #           *dcp X,ind       CPY zpg          CMP zpg          DEC zpg          *dcp zpg
C8               INY impl         CMP #            DEX impl         *axs #           CPY abs          CMP abs          DEC abs          *dcp abs
D0               BNE rel          CMP ind,Y        *kil             *dcp ind,y       *nop zpg,x       CMP zpg,X        DEC zpg,X        *dcp zpg,x       
D8               CLD impl         CMP abs,Y        *nop             *dcp abs,y       *nop abs,x       CMP abs,X        DEC abs,X        *dcp abs,x

E0               CPX #            SBC X,ind        *nop #           *isc X,ind       CPX zpg          SBC zpg          INC zpg          *isc zpg
E8               INX impl         SBC #            NOP impl         *sbc #           CPX abs          SBC abs          INC abs          *isc abs
F0               BEQ rel          SBC ind,Y        *kil             *isc ind,y       *nop zpg,x       SBC zpg,X        INC zpg,X        *isc zpg,x       
F8               SED impl         SBC abs,Y        *nop             *isc abs,y       *nop abs,x       SBC abs,X        INC abs,X        *isc abs,x

[blargg]

Unofficial instructions; they are far from undocumented.

I thought SMB eventually sits in a tight loop, with the game running from NMI, and IRQ never used.

[ember]

There are a few exceptions though, some games use the built-in IRQ feature of the DMC channel to do split screens, such as Time Lord, Mig 29 Soviet Fighter, and Fire Hawk.
And Chun Soft's really early games (Door Door, Dragon Quest, and Dragon Quest II) use the APU Frame IRQ to drive the music engine of the game.

Hi Dwedit, thx a lot for the information, the opcode table looks pretty useful.
To implement both APU-IRQ and MMC-IRQ, should i 'and' the 2 IRQ wires to 1-bit-width wire first, then connect it to CPU?

[ember]

Unofficial instructions; they are far from undocumented.

sorry "offical" is my phrase.
btw, any difference between "unoffical" and "undocumented" here? i don't know....
the "offical" instuments in my post are the instruments listed in http://nesdev.com/6502.txt
maybe they're called "documented"...

[tepples]

The unofficial opcodes were "undocumented" in MOS Technology's 6502 datasheet, but enthusiasts later documented them thoroughly. A few are rawther useful to programmers, and a few are unstable (dependent on temperature, line noise, and the like) because of analog effects related to how a bus conflict interacts with the decimal mode addition circuit. First, I'd recommend emulating enough to get the behavior of nestest.nes to match Nintendulator's log.

should i 'and' the 2 IRQ wires to 1-bit-width wire first, then connect it to CPU?

Yes. This is called open-collector behavior: a resistor weakly pulls /IRQ up to 5 V most of the time unless one of the devices on the bus drives it down to GND.

And for a demo of what's possible with abuse of the DMC IRQ, try my split and letterbox tech demos.