INES Mapper 052

[FARID]

The information on the NESDEV WIKI about the registers of INES Mapper 052 is wrong
Here is the correct information :

$6000-7FFF
D7.... ....D0
ABCD EFGH
A (D7) : LATCH [0:En 1:Dis]
B (D6) : CHR Size [0:256 1:128]
C (D5) : CHR bit 1
D (D4) : CHR bit 0
E (D3) : PRG Size [0:256 1:128]
F (D2) : PRG bit 2 + CHR bit 2
G (D1) : PRG bit 1
H (D0) : PRG bit 0

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And here are some older info about mapper 52 :

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Mario 7 in 1
7 bit 0
---------
xABC DEFG

x- not used
A- CHR ROM bank size. 1=128K, 0=256K
D- PRG ROM bank size. 1=128K, 0=256K
G- PRG ROM bank "part" (for 128K banks)

E,F- PRG ROM 256K bank

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Registers of Gold 7 in 1 HIK AR456
1000 0000
1110 1010
1111 1011
1100 1100
1101 1101
1110 1110
1111 1111

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Registers of 1997 SUPER HIK 8 IN 1 EW-800
1101 1000
1100 1001
1110 1010
1111 1011
1100 1100
1101 1101
1110 1110
1111 1111

*************************************************************

From #nesdev IRC :
[19:35] <thefox> XACCYBPP
[19:35] <thefox> BPP = 3 bit PRG bank selection, selects a 128K prg bank
[19:35] <thefox> Y = PRG size selection, 0 = 256, 1 = 128
[19:35] <thefox> BCC = 3 bit CHR bank selection, selects a 128K prg bank
[19:35] <thefox> A = CHR size selection, 0 = 256, 1 = 128
[19:35] <thefox> X = always 1

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For emulation
Cbank = (E*4 + B*2) OR (A and C) OR (!A and MMC3C)
BTW, bit7 of the extra banking register is used for locking further bankswitching, games doing this when using SRAM area in case tot interfere with the running program...
the same way, bit7 of A001 register of MMC3 used to enable banking at the cartridge start...
anyway, there isn't much useful for emulation, since actually can beignored

*************************************************************

It is possible to remake this kind of cartridge by using 74HC161 as a latch

[lidnariq]

Do you know whether writing to the the banking register additionally writes to PRG RAM? Or, while the 128s bit is clear, is RAM not writeable?

[FARID]

Do you know whether writing to the the banking register additionally writes to PRG RAM? Or, while the 128s bit is clear, is RAM not writeable?

Do you want to use PRG-RAM on this kind of cartridges?
Maybe we can control PRG-RAM by using its CS2 (pin26)
It seems the best way is to use A bit to enable / disable it along with Latch :
In the menu --> A is low --> Latch is enabled --> PRG Ram is disabled
In the game --> A is high -> Latch is disabled --> PRG Ram is enabled

[lidnariq]

Exactly what you said. I was wondering if you knew whether any multicarts actually did that?

We believe that it is the 128s bit that prohibits further writes; do we know whether it additionally enables RAM? Or is PRG RAM simply always enabled, but one doen't care because you only ever write a single value to the not-battery-backed multicart register first?

Kevtris's dumping notes show the presence of the RAM, but are low resolution and don't mention anything.

[FARID]

I am not that much exprienced on SRAM and battery
I have never messed up with those parts
so I have no idea what you are talking about
Also what do you mean by 128 bit?

By the way my 1997 SUPER HIK 8 IN 1 EW-800 cartridge seems to designed to use PRG-RAM but it is not used on nekketsu kunio games
Some of its important pins are like this :

PRG-RAM /WE (pin27) --> MMC3 WRAM /WE
PRG-RAM CS2 (pin26) --> +5V
PRG-RAM /OE (pin22) --> GND
PRG-RAM /CS1 (pin20) -> MMC3 WRAM /CE
Also there is no WRAM CE on its MMC3 because PRG-RAM CS2 (pin26) is connected to +5V all the time!
Its MMC3 is glop top and its pinout is very similar to AX5202P and seems that its WRAM CE is connected to CHR A18!
PRG A19 + CHR A19 are connected to the glop top MMC3 which seems to be pin39 of AX5202P which is marked as NC(For Now)!

And here is the menu code of 1997 SUPER HIK 8 IN 1 EW-800

[lidnariq]

Also what do you mean by 128 bit?

What you called "D7" at the top of your original post. (2^7 = 128)

PRG-RAM CS2 (pin26) --> +5V

That makes it sound strongly like "all writes to the banking control register also go to RAM"

Thank you!

[FARID]

But maybe this PRG-RAM is controlled by its /CS1 or /WE
I know it is a little weird but I feel using 128 bit + NOT Gate + /CS1 can also control PRG-RAM

[lidnariq]

But a not gate isn't sufficient; it would need to both pay attention to Q7 (the latched most significant bit) as well as the MMC3 clone PRG RAM /CE.

It'd need some kind of digital comparator (A>B), given that Q7 is apparently not connected to the PRG RAM.

That logic could all be part of the same silicon die, but the only way to test that is a copynes or kazzo and some kind of logic probe. And I can't come up with a good reason for them to add the extra logic to prohibit writes to RAM, given that the games probably initialize it later.

[FARID]

And I can't come up with a good reason for them to add the extra logic to prohibit writes to RAM, given that the games probably initialize it later.

So it doesn't matter to write to a SRAM which is not battery backed, right?

And any idea why isn't WRAM CE connected to PRG-RAM CS2 (pin26)?
Is it used for some other purpose?
Is it possible to use WRAM CE to generate the clock signal of latch instead of using WRAM /CE?
In that case it needs an active low TTL?
Or 74HC161 with its active high clock can be operated?
Maybe both WRAM CE + CPU R/W are used as decoder to generate the clock signal?

[lidnariq]

I originally thought the WRAM +CE pin out of the MMC3 would have been nothing more than the latched value written to $A001.D7, but that clearly can't be true: NES-TKROM (e.g. Kirby's Adventure) doesn't connect WRAM /CE at all! And looking more closely, it looks like probably both WRAM +CE and WRAM /CE include M2...

So it doesn't matter to write to a SRAM which is not battery backed, right?

No, unless the game does something silly like "failing to initialize memory", possibly because the pirates removed it...

And any idea why isn't WRAM CE connected to PRG-RAM CS2 (pin26)? Is it used for some other purpose?

Ease of routing, maybe? Reducing number of output drivers in the MMC3 clone? It's the same signal, just with inverted voltages, so whether a peripheral is connected to WRAM +CE or /CE is only a matter of the logic it needs, not how, when, or where it appears.

Is it possible to use WRAM CE to generate the clock signal of latch instead of using WRAM /CE? In that case it needs an active low TTL? Or 74HC161 with its active high clock can be operated?

In the NES, M2 rises (and /ROMSEL falls) before the data bus actually asserts the value to be written, so I'd be skeptical of anything that latched the value on the rising edge of +CE or falling edge of /CE. So a 74'161-based design might have to use /CE instead of +CE.

Maybe both WRAM CE + CPU R/W are used as decoder to generate the clock signal?

Unless you do that, of course.

[aquasnake]

according to the wiki decription:

Code: Select all

   $6000-7FFF:  [WMCC SBPP]  Multicart reg
     P = PRG Block (bits 1,0)
         = PRG A18 and A17
     B = CHR+PRG Block Select bit (PRG and CHR bit 2)
         = CHR and PRG A19
     S = PRG Block size (0=256k   1=128k)
         = 0=PRG A17 comes from MMC3  1=A17 comes from this register
     C = CHR Block (bits 1,0)
         = CHR A18 and A17
     M = CHR Block size (0=256k   1=128k)
         = 0=CHR A17 comes from MMC3  1=A17 comes from this register
     W = 1=Disable multicart register and enable RAM
         0=allow further writes to multicart register

this mapper can be tried to expand its function, which can combine a multi-rom((256+256)*n or (128+128)*2n) up to 1024 Mega bits.
the multicart will not simply be a 4-in-1 or 8-in-1 any longer, it would be a great 256-in-1 or 512-in-1.
although prom and crom are fixed to 256KB/128KB and they do waste some memory spaces, this mapper is easier to design with a few 74 logic devices than mapper268 or mapper45.

here it is:

Code: Select all

   $5000-5FFF:  [.BBB BBBB]  Multicart reg
     B = CHR+PRG Block Select bit (PRG and CHR bit[9:3])
         = CHR and PRG A[26:20]
     
     first set $5xxx, next set $6xxx(include "W")
     default status when power on: all registers remain zero