SRAM /CS

[qwertymodo]

Alright, how does this look? The SRAM256K part is the DIP-28 footprint, so the /CE line is the signal coming in from the decoder, and the CE with the bar over it is the actual pin on the FRAM chip. I probably could have better optimized the PCB layout by selecting which gates to hook up to what based on physical location, but the traces are simple enough I didn't bother.

[whicker]

Looks great.
As far as I can determine with my "chip being upside-down and rotated 180" sense, it appears to be wired correctly.

Like all unused gates, I'd just recommend you tie the two unused inputs of gate "D" to Vcc or Gnd. I'd recommend GND because I think you have a ground fill super close to those pins anyway.

[qwertymodo]

The nice thing about EAGLE is that if the schematic is correct, it connects the PCB pins for you (you have to do the actual tracing, but it knows what's supposed to connect to what, so you can't accidentally connect 2 pins that aren't connected on the schematic or it yells at you). I'll go ahead and ground the unused gate inputs.

[lidnariq]

You wanted this circuit instead:

circuit.png (850 Bytes) Viewed 6478 times

For minimal routing difficulty, I'd probably either tie the 2nd (pins 4-5) NAND gate to ground or the 4th (pins 12-13) NAND gate to vcc.

[qwertymodo]

Good catch, I forgot NAND wasn't associative...

[qwertymodo]

Hey whicker, how would you modify your schematic for a single, 16Mbit ROM? Where would you connect the ROM A20 line? Would you just hook it straight up to pin 46 on the cart edge? That's how the MAD-1 boards seem to do it... but the MAD-1 is decoded off of BA4 and BA5, where your schematic is decoding off of BA5 and BA6 (you call them CA21 and CA22). Also, would I then need glue logic between the 139 and the ROM /CS line? Y0 NAND Y1, maybe?

[whicker]

I'll answer this better tomorrow.
I just got back from anime central.

Yes A20 would just go from the chip to the cart edge.
You still need chip select logic so that the chip isn't always sending out data.
It's not Y0 nand Y1.

[whicker]

Alright, A20 from the flash chip goes to cart edge pin 46.
Chip Select on the flash chip would be the output from an OR gate:

Flash /CS = pin 49 (/ROMSEL) OR pin 47 (S-CPU A22)

In the exact diagram, you could also use the other half of the 74139 chip to make the OR function.
2A input tied to GND, 2B input still CA22, 2G still /ROMSEL, use output 2Y0 for chip select.
That's if you're actually using a 74139

[qwertymodo]

Alright, A20 from the flash chip goes to cart edge pin 46.
Chip Select on the flash chip would be the output from an OR gate:

Flash /CS = pin 49 (/ROMSEL) OR pin 47 (S-CPU A22)

In the exact diagram, you could also use the other half of the 74139 chip to make the OR function.
2A input tied to GND, 2B input still CA22, 2G still /ROMSEL, use output 2Y0 for chip select.
That's if you're actually using a 74139

I am using a 74139, but I'm trying to see if I can get all of the decoding working with just the 74139 and the 1 extra NAND gate I have available on the 7400.

So (just to talk this through and see if I'm getting this right):

ROM_CE = /CART OR A22 (/ROMSEL seems like a misnomer since when it's high, it disables both ROM and RAM, so it really acts as a /CARTSEL)
RAM_CE = (/CART OR (A21 NAND A22) OR A15) OR (/RD AND /WR)

Now, from the previous discussion, /CE can be simplified to
RAM_CE = NOT (/CART OR (A21 NAND A22) OR A15) NAND (/RD NAND /WR)

So, we build ROM_CE from the first half of the '139, and use the second half as a 3-input or for the (/CART OR (X) OR A15) where X is A21 NAND A22 (the 4th NAND gate).

If I actually got all of that right, this should do it...

[whicker]

After extensively looking at this, I can't find a reason why what you have wouldn't work.

The only caveat is that the FeRAM maps into banks 60h-6Fh as well as banks 70h-7Dh. I don't forsee this being a problem. Bank 6xh with A15=0 is ordinarily for the DSP-1 or whatever coprocessor for certain rom sizes. Shouldn't matter for what you're using it for.

The long chain of gates doesn't seem like it will glitch in a way to cause issues, and games are supposed to access Battery RAM in the slow speed area anyways.

Would there be a way to save maybe 1 or 2 nand gates? probably, but let's not worry about it.

[qwertymodo]

I looked at your schematic again, and mine maps bank 6xh the same way yours does. Bank 6xh means BA5 and BA6 (A21/A22) are both high. In your schematic, that selects Y3 low, combined with A15 low selects RAM_CE unless both /RD and /WR are high.

[whicker]

I looked at your schematic again, and mine maps bank 6xh the same way yours does. Bank 6xh means BA5 and BA6 (A21/A22) are both high. In your schematic, that selects Y3 low, combined with A15 low selects RAM_CE unless both /RD and /WR are high.

Yes, exactly.
I was okay with it not perfectly matching the mapping. It never caused issues (and it shouldn't). That area would be open bus otherwise.
I was trying to make the circuit have the bare minimum components to run, a goal you probably agree with.
I was just warning you of anything I knew was off, in case you were about to make a run of 10,000 of these or something.

[qwertymodo]

Thanks for the help, guys. Just got the standalone PCB's in, and so far my Zelda: Parallel Worlds cart is working great with F-RAM on-board!