Question about writing to internal PPU cgram mid frame (involving overriding the bus in the cartridge))

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spaceharrier
Posts: 40
Joined: Wed Jan 19, 2022 9:52 am

Question about writing to internal PPU cgram mid frame (involving overriding the bus in the cartridge))

Post by spaceharrier »

Hello,

I am an embedded software engineer and I have spent a few months familiarizing myself with the NES technical doodads the 6502 instruction set, and have written some demo code in assembly to get my feet wet.

One thing I that piqued my interest was when I was looking at the schematics of the NES, related to the DBE and r/w lines for ppu/cpu communication.

Previously, I had seen a demo where someone got a full color palette on the screen. This achieved about 1 color change per 9 pixels, which makes sense giving the master clock division and number of cycles needed for a data write.

I had a thought I would like to explore, in this regard. In the atari 2600 dev scene, an advanced technique used to increase memory bandwidth is to have an extra piece of hardware override the data bus during writes (basically the cpu writes FF's and the hardware in the cartridge pulls appropriate bits down) They refer to this technique as "bus stuffing."

I notice the cartridge port in the NES has access to PHI2, which needs to be high for the DBE line of the PPU to be active.

Based on my terrible math:

The CPU has one cycle every 12 master cycles. Phi2 is 5/8 of that time, which means that from roughly cycles 4.5 - 12, phi2 is high.
Write read is active high.

If I were to have some extra technical doodad in the cartridge intercept writes to the cgram, and then strobe the M2 and R/W line, would I be able to write to the CGRAM multiple times per CPU clock cycle (whilst pulling appropriate address and data bits to zero to form the correct address/data writes)? If so, doing this would have the potential for me to write palette entries fast enough to increase the total number of colors per line.

Has anybody experimented with such already?
lidnariq
Posts: 11432
Joined: Sun Apr 13, 2008 11:12 am

Re: Question about writing to internal PPU cgram mid frame (involving overriding the bus in the cartridge))

Post by lidnariq »

The PPU internally synchronizes things on pixel edges (it uses two biphase clocks at 5.4MHz) so you can't "just" override M2 and call it a day.

Unfortunately, the PPU treats CGRAM and "normal" PPU RAM writes almost the same way, so there's still a large delay of 6-9-ish pixels after the CPU starts/ends the write to when the write actually happens.
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