6502 in Logisim

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org
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Joined: Tue Aug 07, 2012 12:27 pm

6502 in Logisim

Post by org »

The 6502 circuit for Logisim has been completed.

https://github.com/emu-russia/breaks/tr ... 02_logisim

To run the simulation:
- Load the test program into RAM (e.g. visual6502.hex)
- Set RDY = 1, /NMI = 1, /IRQ = 1, /RES = 0
- Run several cycles until the 6502 goes into standby mode
- Set /RES = 1

The processor will then continue to execute as usual. The BRK reset sequence will be initiated first, then it will go to the address specified in the Reset interrupt vector and start execution of the demo program.

The circuit contains a couple of workarounds, mostly it concerns bi-directional buses, which are not supported in Logisim:
- All bidirectional buses are divided into two (Bus In / Bus Out)
- Special handling of SB/DB and SB/ADH commands that connect bi-directional buses SB, DB and ADH (found in BUS_MUX_HACK circuit)
- Special processing of the very first half-cycle, when the processor "goes crazy". In this half cycle all internal buses must be cleared (found in PRECHARGE circuit).
Attachments
6502_logisim_bogus_board.jpg
alu.jpg
M6502_Logisim.jpg
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