Ben Boldt wrote: ↑Sat May 14, 2022 6:40 pm
We should have a challenge. Design 100% compatible MMC1, only use 74xx chips (any, including shift registers, rare ones etc), minimum # of chips wins.
How many do you think it takes? What’s realistic?
The problem is that doing so is completely useless. Many chips technically existing in the 74xx series are rare or even very rare. You could play and make a schematic with them but you'd never be able to even try if this works. And even then, to get the exact replica of an MMC1, you'd need at least 5 chips to get just the shift register to behave the same. The major problem is the shift register who is 5 bits, and internal registers are 5 bits, when most chips have 4 of the same element. This thing alone increase the # of chips needed to get it done.
I already saw your project. actually the mmc1 register is the difference of it not being so simple. but I believe that to run a game only CHR PRG rom. Be practical using TTL , the SXrom mappers are quite peculiar .
I think there is room for everything. each project sums + the global retro console community
your code is very well improved beautiful.
INL historically asserted that every existing MMC1 game only uses a subset of the functionality, so any one given game can fit into a single 36-macrocell Xilinx CPLD.
(The full amount of state needed for the MMC1 is only 24 bits, but the other macrocells are needed for the glue logic)
The problem is that the only Discrete Logic mapper with 4+4 banking is NINA-001. It's a lovely mapper for that reason by itself, but it means that there's no ready-to-use mapper for, say, mirroring control and 4+4 CHR banking. I could have sworn the wiki used to describe some de-serialized MMC1 mapper variant but I can't find it now.
Mmc1 series is a huge family. Some sub-mappers do not have a superset-subset relationship, so the implementation consumes logic resources and has to be isolated by state machine, which leads to the discretization of mapper. One or two sub mappers can be realized by 74 series logic gates, but it is impossible to emulate all of family
Why still insist on using 74? I think this is a meaningful topic. Building circuits with 74 logic gates has less learning cost
aquasnake wrote: ↑Fri May 20, 2022 7:38 pm
Mmc1 series is a huge family. Some sub-mappers do not have a superset-subset relationship, so the implementation consumes logic resources and has to be isolated by state machine, which leads to the discretization of mapper. One or two sub mappers can be realized by 74 series logic gates, but it is impossible to emulate all of family
Why still insist on using 74? I think this is a meaningful topic. Building circuits with 74 logic gates has less learning cost
a xilinx would be ideal because the ES ports accept simultaneous 3v/5v without level shifters
there's a mapper made by the Latin of the consoles for siempre that they say it works