While analyzing an old ISA card which is a bridge between PC and a DIP programmer, I found some interesting idea here:
Parallel register (74174) is connected in such a way, that it makes a shift register out of it.
After a first read (or write) to a specific location of memory (ADDR=1), 1 is latched into Q1 (and 0 to I/O CH RDY)
Then after second cycle, this 1 is shifted into Q2, then Q3, then Q4, then Q5 and then Q6. And when Q6 = 1, it asynchronically clears this shift register,
releasing I/O CHR_RDY (goal was to hold CHR_RDY low for 6 cycles).
This idea might be interesting when trying to implement MMC1 from discretes.
Shift register from parallel register
- krzysiobal
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