Questions about the Z80 CPU

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Drag
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Questions about the Z80 CPU

Post by Drag »

Hey all, I'm working on a z80 assembly reference as a way to both brush up on it and to aggregate a bunch of info into one place. It's coming along fine, but I've run into some weird parts where it's easier to just ask about them instead of trying to assume things. :P

Right now, I'm trying to create cycle tables which break down what the clock-by-clock bus activity for each opcode is.

For the indexed bit shifting opcodes, e.g. RLC (IX+$nn), I've found the following documented cycle timing from here:

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							MACHINE CYCLE
	INSTRUCTION	BYTES   M1		M2		M3		M4		M5
	RLC (IX+d)	4	OCF(4)/OCF(4)	OD(3)		IO(5)		MR(4)		MW(3)
This is a 4-byte opcode that does a read-modify-write operation on memory, so aren't there supposed to be 5 reads? My guess is that M3 contains the read for the fourth opcode byte, and then I'm not sure what the timing of the read is (I'd assume the first three T-states are just the standard memory read timing, and then the last two T-states are just bus-idle). Can anybody correct me on this?

Edit: Answer: (Post) According to this helpful document, the fourth opcode byte is indeed read during M3; the first three T-states are a normal read cycle, and then two idle T-states occur after, before M4 starts. The document also explains the timing for LD (IX,d),n, which is completely absent from the documentation I was using.
Last edited by Drag on Tue Sep 06, 2022 11:11 am, edited 2 times in total.
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aa-dav
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Re: Questions about the Z80 CPU

Post by aa-dav »

I don't know for sure, but keep in mind that all extended instructions with IX/IY are prefixed instructions with HL register. It's just some kind of temprorary register change with side-effect of additional byte offset with indirect addressing mode. DD and FD prefixes just tell CPU to work with IX/IY instead of HL and use byte prefix if indirect addressing mode is present. Encoding of effective instruction is the same as for HL.
So, compare table entry with the same instruction with HL, that is:

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RLC (HL)	2	OCF(4)/OCF(4)	MR(4)		MW(3)
I think that M2/OD(3) in IX variant is reading byte offset (fourth byte of instruction) and M3/IO(5) is forming of 16-address for indirect read/write.
P.S.
I got encoding of this table and yes, this seems stange. Also comparing with INC (IX+d) raises questions due to the same T-clocks despite of absence of 1 byte prefix... Hm...
P.P.S.
Hm, it's even more interesting because encoding of RLC (YX+d) is DD CB d 06, that is factual opcode is the LAST fourth byte of instruction. It's reading really has to be in M3/IO cycle along with address calculation (?!). It's really very strange.
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aa-dav
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Re: Questions about the Z80 CPU

Post by aa-dav »

I've found detailed description of this oddities with timings: https://floooh.github.io/2021/12/06/z80 ... -cb-prefix
It really fetches 'actual opcode' in M3. :)
Drag
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Re: Questions about the Z80 CPU

Post by Drag »

Wow! That document is excellent. Thank you so much! :D
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