Right now, I'm trying to create cycle tables which break down what the clock-by-clock bus activity for each opcode is.
For the indexed bit shifting opcodes, e.g. RLC (IX+$nn), I've found the following documented cycle timing from here:
Code: Select all
MACHINE CYCLE
INSTRUCTION BYTES M1 M2 M3 M4 M5
RLC (IX+d) 4 OCF(4)/OCF(4) OD(3) IO(5) MR(4) MW(3)
Edit: Answer: (Post) According to this helpful document, the fourth opcode byte is indeed read during M3; the first three T-states are a normal read cycle, and then two idle T-states occur after, before M4 starts. The document also explains the timing for LD (IX,d),n, which is completely absent from the documentation I was using.