SPC700 Timer Reset Question

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KungFuFurby
Posts: 275
Joined: Wed Jul 09, 2008 8:46 pm

SPC700 Timer Reset Question

Post by KungFuFurby »

When the SPC700 timers are reset (by writing anything to CONTROL), do the TnOUT registers also reset, or do they only reset when read from the TnOUT registers?

I have an idea in my mind to create a 12-bit timer and I would like to know if I can simply perform a "phase reset" with the timer without affecting the TnOUT registers. If I can do that, then that saves me an edge case (and I get to read them all within (4 cycles per sample * 4 samples per 8khz timer tick) 128 cycles before the next tick, which is plenty of time for me to get all 12 bits).
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jeffythedragonslayer
Posts: 344
Joined: Thu Dec 09, 2021 12:29 pm

Re: SPC700 Timer Reset Question

Post by jeffythedragonslayer »

Here's what anomie has to say regarding the CONTROL register bits 0-2, bold emphasis mine:
anomie wrote: 012 = Enable timer 0, 1, or 2. See registers $00fa-f. When
transitioning from 0 to 1, the timer Stage 2 and 3 counters are
both reset to 0.
Note however that the Stage 1 'counter' is not
reset.
As stage 3 is the 4-bit output it appears the answer is yes, they are reset.
KungFuFurby
Posts: 275
Joined: Wed Jul 09, 2008 8:46 pm

Re: SPC700 Timer Reset Question

Post by KungFuFurby »

Well, well, well! I'm pleasantly surprised someone replied to a six year old topic I created! Yeah, multiple sources say yes these days: fullsnes also tells me TnOUT is set to zero and the divider is reloaded.

I abandoned my 12-bit timer idea due to other issues when I initially attempted to implement this into my custom sound driver, so I did something else with one timer instead.
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jeffythedragonslayer
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Re: SPC700 Timer Reset Question

Post by jeffythedragonslayer »

What made 12-bits impractical?
KungFuFurby
Posts: 275
Joined: Wed Jul 09, 2008 8:46 pm

Re: SPC700 Timer Reset Question

Post by KungFuFurby »

The main problem I had was reading three timers in the first place (when one of them can be up to 16 ticks off because I can't grab them all in one opcode): I can read two at once with a single word opcode, though I need to double check the timing to ensure that once again a 4-bit timer overflow doesn't happen on the edge cases), and naturally I still need to combine them after reading them.

I ended up just simply using a single 4-bit timer (though at the cost of increased polling) because it was far easier for me to use a single ADC opcode against a raw timer value and send it directly to a memory location. For any extra bits to track, I just simply use a second ADC opcode with zero as the parameter, taking advantage of carry overflows.

If I remember my settings correctly, this is what my TnDIV settings were when making the 12 bit timer...
T0DIV - 0 or 256
T1DIV - 16
T2DIV - 8 (due to being 64khz: this makes it effectively 8 khz)

So I just remembered that TnOUT was reset by two methods: directly reading them, and the CONTROL register. The latter one I was counting on, but zeroing out all of the TnOUT registers again almost immediately after reading means that I incur a small delay timer-wise since I zero them out again.
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