OAM DMA Circuit

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org
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Joined: Tue Aug 07, 2012 12:27 pm

OAM DMA Circuit

Post by org »

oam_dma_parts.png
I want to tell you a little bit about how the OAM DMA controller circuit works.

OAM DMA is one of the two DMA controllers inside the APU.

The signals are:
- ACLK and #ACLK: APU Clock.
- PHI1: The first half cycle of the CPU
- R/W: CPU R/W signal (operating mode; 1: Read Mode, 0: Write Mode)
- RUNDMC: OAM DMA lockout signal from DPCM DMA side. Used to suspend OAM DMA when two DMAs intersect
- SPRS: A signal that enables OAM counter (low 8 bits of the address). The signal is silenced by RUNDMC.
- SPRE: OAM counter overflow signal. Used to determine if an OAM DMA is complete.
- DMCReady: The DPCM DMA ready signal. Combined with the OAM DMA ready signal (oamdma_rdy) to produce the RDY signal for the 6502
- SPR_CPU: Perform a read byte in the DMA Buffer at the OAM Counter address. The signal is silenced by RUNDMC.
- SPR_PPU: Write the value in the DMA Buffer to register $2004. The signal is silenced by RUNDMC.

Main circuit components:

RS-FF to store a write event to register $4014 (signal W4014)
This RS-FF is set when write operation W4014 is activated. The W4014 signal, like the other RegOps, is active only during PHI2 (second half of the CPU cycle).
This RS-FF is cleared by the RES signal and also immediately after the start of OAM DMA (when the NOSPR signal becomes 0) ("autocleared")

CPU Read Cycle Detector
Made simple: `read_cycle = (R_W == 1) & (PHI1 == 0)`
The need for the Read Cycle detector is due to the fact that the CPU ignores a low RDY signal during write cycles.

OAM DMA start event is considered to have occurred if:
- A write event has occurred to register $4014.
- Processor went into Read Cycle.

RS-FF "DMA Enabler"
Latches the OAM DMA start event (DOSPR signal). Cleared by SPRE signal and during reset (RES).

"No Sprite DMA" latch (nospr_latch)
This latch remembers the last DMA Enabler value, but only opens during #ACLK. Opening this latch during #ACLK is exactly related to the case of "unaligned DMA": even if all OAM DMA start events have been detected and stored on the DMA Enabler - the actual OAM DMA will not start until #ACLK has occurred.

RS-FF DirToggle
A regular FF that constantly changes its value from 0 to 1 and back, thus determining the direction of the OAM DMA.

RDY Generator
The RDY signal for the processor is simply the logical AND of signals oamdma_rdy and DMCReady.

DMA Process

The NOSPR signal is the main driving force behind all OAM DMA. When NOSPR is 0 - the OAM DMA circuitry performs its activities to provide the OAM DMA process.

The OAM DMA process consists of the following activities:
- Alternating DMA direction change (DMA DirToggle), which eventually generates the SPR_PPU and SPR_CPU signals
- Activating the SPRS signal to turn on the OAM Counter (so that the OAM DMA address keeps increasing).

These processes are "silenced" by the RUNDMC signal.

DPCM DMA and OAM DMA Interaction

DPCM DMA affects the operation of OAM DMA in only two ways:
- The RUNDMC signal "silences" (nulls) the OAM Counter counting signal (SPRS) and the signals for OAM DMA direction (SPR_CPU/SPR_PPU). Thus, only the OAM Counter is actually suspended. DirToggle continues to work, so you need to maintain precise timing of the RUNDMC signal, so that at the time of RUNDMC "push-back" - DirToggle took the same value as before;
- DMCReady signal is simply "forwarded" to the RDY terminal of the processor. Of course, if oamdma_rdy signal is 0, then DMCReady signal has no effect. This can happen, for example, when DPCM DMA terminates "inside" OAM DMA: DPCM DMA will say DMCReady=1, but processor will not wake up anyway, because oamdma_rdy signal is still 0 (OAM DMA has not finished)

I believe this tip will help authors of emulators to accurately implement all DMA mechanisms in APU. Thank you.

EDIT: I have added waves to show when OAM DMA starts and ends.
Attachments
oam_dma_start.png
oam_dma_last.png
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jeffythedragonslayer
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Joined: Thu Dec 09, 2021 12:29 pm

Re: OAM DMA Circuit

Post by jeffythedragonslayer »

RUNDMC ですか ?

Anyway, why is the OAM DMA controller inside the audio chip though, since it has to do with video stuff?
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Quietust
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Re: OAM DMA Circuit

Post by Quietust »

jeffythedragonslayer wrote: Thu Feb 09, 2023 7:00 pm Anyway, why is the OAM DMA controller inside the audio chip though, since it has to do with video stuff?
Given that it needs to pause the CPU's execution and take over its bus to copy 256 bytes to $2004, where else would you expect it to go?
Quietust, QMT Productions
P.S. If you don't get this note, let me know and I'll write you another.
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jeffythedragonslayer
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Re: OAM DMA Circuit

Post by jeffythedragonslayer »

Quietust wrote: Thu Feb 09, 2023 7:16 pm
jeffythedragonslayer wrote: Thu Feb 09, 2023 7:00 pm RUNDMC ですか ?

Anyway, why is the OAM DMA controller inside the audio chip though, since it has to do with video stuff?
Who said anything about the RP2A03 being an "audio chip"? The CPU's in there too, so it makes sense to put the DMA logic in there with it.
Well, my understanding was that the APU is part of the RP2A03, so I expected the OAM DMA controller to be on die with the RP2A03 but not inside the APU part of it.
lidnariq
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Re: OAM DMA Circuit

Post by lidnariq »

There is no "on the 2A03, outside the 6502, and not part of the APU" - the area needed by the APU is something around 60% of the die, the 6502 is something like 20%, and the remaining 19% are the now-missing interval timer from the original one. The remaining 1% is OAMDMA and the joypad registers.
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