This page is extremely hard to understand and leaves me with many questions:
#1: It says that the APU is only ticked on odd CPU cycles, but it also says:
So what this actually means is the APU is ticked on every CPU cycle, but even cycles can only perform memory operations and only odd cycles can perform quarter-/half- frame operations and IRQ signaling. Is this a correct way to interpret this?* If the write occurs during an APU cycle, the effects occur 3 CPU cycles after the $4017 write cycle, and if the write occurs between APU cycles, the effects occurs 4 CPU cycles after the write cycle.
Or can quarter/half events happen on even CPU cycles?
#2: Why are there .5 cycles? Is it trying to say that step 1 occurs on cycles 3728 and 3729 alternating? How would this alternating pattern come into existence when they correspond to odd CPU cycles and 29830 CPU cycles is evenly divisible by 2?
I mean, 3728.5 APU cycles corresponds to 7457 CPU cycles, so it’s going to happen on CPU cycle 7457, then 37287, etc. These are all odd CPU cycles. So why would an alternating pattern emerge, what does the .5 mean, and why is it not clearly explained on the page?
So is it 3728.5 or 3729.5? Are we adding a cycle to 3728.5? Does 3728.5 already have the added cycle baked in?with an additional delay of one CPU cycle for the quarter and half frame signals