Even/Odd cycle detection
Moderator: Moderators
- jeffythedragonslayer
- Posts: 344
- Joined: Thu Dec 09, 2021 12:29 pm
Even/Odd cycle detection
Every 65x instruction takes at least two cycles, but some (like BRK) take an odd number of cycles. Is it possible to write code to detect whether an even or odd number of cycles have elapsed since reset?
Re: Even/Odd cycle detection
Many common instructions take an odd number of cycles. The CPU doesn't provide a way to detect this, but you can use tricks with the APU to identify the current cycle parity. The CPU starts execution in an unpredictable alignment with the APU, though, so if you care about specifically even or odd versus just one parity or the other, you'd need to figure at reset what the alignment is. See the synchronized write methods for the EPSM (DMC DMA, OAM DMA, and controller strobe detection) and DMA for more information.
It is generally easier to answer this kind of question if you say why you want to be able to do this. It's entirely possible that you don't need what you're asking about; off the top of my head, I'm not sure why you'd ever need to know about even vs odd (versus just one or the other parity, and even needing that is atypical).
It is generally easier to answer this kind of question if you say why you want to be able to do this. It's entirely possible that you don't need what you're asking about; off the top of my head, I'm not sure why you'd ever need to know about even vs odd (versus just one or the other parity, and even needing that is atypical).