APU Emulation

Discuss emulation of the Nintendo Entertainment System and Famicom.

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L. Spiro
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APU Emulation

Post by L. Spiro »

https://www.nesdev.org/wiki/APU_Frame_Counter
This page is extremely hard to understand and leaves me with many questions:

#1: It says that the APU is only ticked on odd CPU cycles, but it also says:
* If the write occurs during an APU cycle, the effects occur 3 CPU cycles after the $4017 write cycle, and if the write occurs between APU cycles, the effects occurs 4 CPU cycles after the write cycle.
So what this actually means is the APU is ticked on every CPU cycle, but even cycles can only perform memory operations and only odd cycles can perform quarter-/half- frame operations and IRQ signaling. Is this a correct way to interpret this?
Or can quarter/half events happen on even CPU cycles?

#2: Why are there .5 cycles? Is it trying to say that step 1 occurs on cycles 3728 and 3729 alternating? How would this alternating pattern come into existence when they correspond to odd CPU cycles and 29830 CPU cycles is evenly divisible by 2?
I mean, 3728.5 APU cycles corresponds to 7457 CPU cycles, so it’s going to happen on CPU cycle 7457, then 37287, etc. These are all odd CPU cycles. So why would an alternating pattern emerge, what does the .5 mean, and why is it not clearly explained on the page?

#3:
with an additional delay of one CPU cycle for the quarter and half frame signals
So is it 3728.5 or 3729.5? Are we adding a cycle to 3728.5? Does 3728.5 already have the added cycle baked in?


L. Spiro
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Quietust
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Re: APU Emulation

Post by Quietust »

The CPU's clock is divided into two phases, each one running at half speed, and those phases are used to run most of the APU. Some operations are driven by the first phase while other operations are driven by the second phase, and this is what results in the "half APU cycles" in various places.

For example, Sprite DMA always uses the first phase to perform reads and the second phase to perform writes, so depending on when you trigger it, it needs to wait 1 or 2 cycles to become properly "aligned".
L. Spiro wrote: Sat Feb 04, 2023 5:04 am So what this actually means is the APU is ticked on every CPU cycle, but even cycles can only perform memory operations and only odd cycles can perform quarter-/half- frame operations and IRQ signaling. Is this a correct way to interpret this?
Something like that, yes.
Quietust, QMT Productions
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L. Spiro
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Re: APU Emulation

Post by L. Spiro »

So when it says APU cycle 3728.5, I should just map that to CPU cycle 7457 and call it good?

What about the additional delay?
with an additional delay of one CPU cycle for the quarter and half frame signals

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Fiskbit
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Re: APU Emulation

Post by Fiskbit »

Regarding even/odd CPU cycles, I believe this is misleading terminology and should be retired from the wiki. This is trying to express that certain things only happen on one half of the APU clock or the other. However, my understanding is that the alignment between the CPU and APU is effectively random; that is, the CPU can begin execution on either half of an APU cycle. Therefore, timing of things like the frame counter, DMA, joypad OUT toggles, and other functionality that runs off the APU clock will vary across resets.
L. Spiro
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Re: APU Emulation

Post by L. Spiro »

I know that the PPU alignment across resets is random, so this applies to the APU too even though it is part of the CPU (or clocked by the CPU, or-?)?

Accuracy is goal of my emulator, and I am going sub-cycle–accurate. My PPU, CPU, and APU each have their own timing counters and it’s easy to misalign them to recreate the effects of reset, but I would need to know the exact details behind the misalignment.

My CPU doesn’t clock my APU, so I am using even/odd cycles as shorthand for “every other cycle”.
I’d like to know the details behind the misalignment so that I can emulate it accurately but I will still probably be referring to them as even/odd cycles for conceptual convenience.


So, everything about my last post? CPU cycle 7457? Additional delay?
When it gives a .5, that’s just trying to say that it always happens on the second half of the APU clock? But again, isn’t that implicit if I just call it CPU cycle 7457? Or is there a detail I am missing? Regarding the misalignment, my guess is that once misaligned, everything falls to one side of the cycle or the other, which is what will happen no matter how I misalign them in my implementation, so maybe the details aren’t so important, but I will let someone verify that.


Regards,
L. Spiro
Fiskbit
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Re: APU Emulation

Post by Fiskbit »

The CPU/PPU alignment is random at power-on and random whenever the PPU is reset because the PPU's clock divider is affected by reset; however, not all consoles reset the PPU on reset, so console reset may preserve CPU/PPU alignment. NES-001 and FamicomBox are the only consoles I'm aware of that reset the PPU on console reset, changing the alignment.

It's not known if the 2A03 powers on with a fixed CPU/APU alignment, but the 2A03 clock continues to run during CPU reset. Thus, the alignment will vary depending on when the it comes out of reset. For a console reset, this is effectively random because reset length is controlled by the user. For power-on, this is suspected to be random based on the CIC, capacitor precision, and other analog behavior.

I don't know the rest here, but would guess that 3728.5 does imply 7457 CPU cycles. I don't know how to interpret the additional delay comment; perhaps the effect is delayed one cycle after the step occurs (i.e. happens on the other half of the APU clock).
posit
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Re: APU Emulation

Post by posit »

From what I can tell, and confirmed with passing all the APU tests I can find, the "additional delay" is just referencing the .5 APU ticks. i.e the not-quarter and not-half frame sequence ticks occur on an integer APU tick.

Agreed about terminology on the wiki - it's not like all the oscillators' timers even run on these APU ticks, such as noise.
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org
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Re: APU Emulation

Post by org »

If it comes in handy, here is a clear diagram of which clocks are inside the APU.
Attachments
apu_clocks.png
L. Spiro
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Re: APU Emulation

Post by L. Spiro »

Sorry for dropping out of the discussion for a bit; I moved back to Japan.

https://www.nesdev.org/wiki/APU_Frame_Counter
Step 4 of mode 0 (Mode 0: 4-Step Sequence (bit 7 of $4017 clear))
Why is “Set if interrupt inhibit is clear” listed on 3 different cycles?
Let’s say I ignore their APU cycle = 2 CPU cycles and just say that 14914 = CPU cycle 29828, 14914.5 = CPU cycle 29829, and 14915 = CPU cycle 29830.
I’m not supposed to actually send 3 interrupts, am I? Isn’t it just supposed to be on cycle 29830? Why are the others listed there and what conditions could cause me to interrupt there instead of on cycle 29830?


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tepples
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Re: APU Emulation

Post by tepples »

As I understand it, it means that even if the CPU acknowledges the interrupt on the first or second of those cycles, the APU will assert another interrupt on the following cycle.
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