Which is the priority?

Discuss emulation of the Nintendo Entertainment System and Famicom.

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Anes
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Which is the priority?

Post by Anes »

If we have sprite dma, irq and nmi. Which is the priority. I suppouse if nmi is enabled comes before irq, but i don't know about sprite dma.
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org
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Re: Which is the priority?

Post by org »

Where did you read that OAM DMA has an interrupt? OAM DMA affects the RDY input of the integrated 6502 core, the effect of which is hard for me to describe in simple words, but in short it suspends the whole core :)
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Anes
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Re: Which is the priority?

Post by Anes »

I didn't say that i read that it was an interrupt. I know it's not an interrupt but if it stall the cpu it mas have a priority
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Fiskbit
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Re: Which is the priority?

Post by Fiskbit »

When the CPU is halted for DMA, the DMA units will finish before the CPU can run again and service any interrupts.

I'm not familiar with the exact behavior regarding interrupt detection, so someone who knows more should correct me if I'm wrong, but I assume the CPU will still latch NMI edges that occur while halted, but won't be checking the IRQ input.
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Anes
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Re: Which is the priority?

Post by Anes »

Talking about sprite dma, the wiki says:
The CPU is suspended during the transfer, which will take 513 or 514 cycles after the $4014 write tick. (1 wait state cycle while waiting for writes to complete, +1 if on an odd CPU cycle, then 256 alternating read/write cycles.)
This:
+1 if on an odd CPU cycle
What does it mean?
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Fiskbit
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Re: Which is the priority?

Post by Fiskbit »

The CPU alternates between get cycles, on which the DMA units can read, and put cycles, on which the DMA units can write. OAM DMA takes one halt cycle, then an optional alignment cycle, and then 256 get/put pairs. That alignment cycle only occurs if the current cycle is a put, because it cannot do reads on a put cycle.

All of this is covered in extreme detail here: https://www.nesdev.org/wiki/DMA
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