Sharp MMC1 Reverse Engineered
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Sharp MMC1 Reverse Engineered
Hello.
MMC1 circuit reconstruction completed:
https://github.com/emu-russia/mappers/tree/main/MMC1
All the materials are there, including the topology and cell layout, as well as an automatically restored Verilog netlist.
MMC1 circuit reconstruction completed:
https://github.com/emu-russia/mappers/tree/main/MMC1
All the materials are there, including the topology and cell layout, as well as an automatically restored Verilog netlist.
Last edited by org on Sat Jun 24, 2023 11:35 pm, edited 2 times in total.
Re: Sharp MMC1A Reverse Engineered
nice work! Can we find out exactly how this works: https://www.nesdev.org/wiki/MMC1#Consec ... cle_writes ?
best regards,
- dink
best regards,
- dink
Re: Sharp MMC1A Reverse Engineered
org just released a logisim schematic. https://raw.githubusercontent.com/emu-r ... ogisim.jpg
On a falling edge of M2 ...
gates 25 and 26 latch NOT(R/W) AND NOT(delayed(/ROMSEL))
which is then ANDed with NOT(delayed(M2))
which is then delayed
and a rising edge of that signal is what latches things in the shift register.
and no I don't understand how that works.
On a falling edge of M2 ...
gates 25 and 26 latch NOT(R/W) AND NOT(delayed(/ROMSEL))
which is then ANDed with NOT(delayed(M2))
which is then delayed
and a rising edge of that signal is what latches things in the shift register.
and no I don't understand how that works.
Re: Sharp MMC1A Reverse Engineered
Logisim adaptation made by andkorzh
Re: Sharp MMC1A Reverse Engineered
I have added a test bench so that you can do your own experiments.Can we find out exactly how this works
https://github.com/emu-russia/mappers/t ... MC1/icarus
As for the ignored-second-write, I am attaching the waves.
Re: Sharp MMC1A Reverse Engineered
So when R/W and /ROMSEL are both low on the falling edge of M2 then the signal goes high. Two consecutive writes will keep that signal high so there is only one rising edge. It needs either a read or /ROMSEL to go high before it can produce a rising edge again.lidnariq wrote: ↑Sat Jun 10, 2023 3:15 pm org just released a logisim schematic. https://raw.githubusercontent.com/emu-r ... ogisim.jpg
On a falling edge of M2 ...
gates 25 and 26 latch NOT(R/W) AND NOT(delayed(/ROMSEL))
which is then ANDed with NOT(delayed(M2))
which is then delayed
and a rising edge of that signal is what latches things in the shift register.
and no I don't understand how that works.
The bit 7 reset is latched at (rising?) edge of M2: (/ROMSEL OR R/W OR NOT(D7)) so every write with D7 set will reset the shift register.
Re: Sharp MMC1A Reverse Engineered
Shift register is never reset. The divider that runs in parallel with the shift register and is responsible for turning on the register decoder is reset. The description on the nesdev wiki does not take this pecularity into account.
Re: Sharp MMC1A Reverse Engineered
Fixed a small inaccuracy: the dffre cell is actually dffrs (set used during MMC1 reset).
https://github.com/emu-russia/mappers/b ... s.md#dffrs
Updated waves for MMC1 reset.
https://github.com/emu-russia/mappers/b ... s.md#dffrs
Updated waves for MMC1 reset.
Re: Sharp MMC1A Reverse Engineered
This wasn't pointed out earlier, but this chip wasn't actually an MMC1A (which looks like this) but a letterless MMC1. However, it still seems to behave the same as the MMC1A.
Quietust, QMT Productions
P.S. If you don't get this note, let me know and I'll write you another.
P.S. If you don't get this note, let me know and I'll write you another.