PPU1 VRAM, Discuss the purpose of VA14

[fabiensanglard]

Hello fellow SNES passionate people,

I am currently studying the SNES PPU and staring at the gorgeous schematics by Jonathon W. Donaldson (https://wiki.superfamicom.org/uploads/s ... _color.pdf).

I can make sense of almost everything except for the shared VA14 line. The PPU1 has dedicated address lines for each VRAM chip, labeled [VAA0-VAA13] and [VAB0-VAB13]. This wiring provides the ability to fetch two different bytes when Mode 7 makes tile data access non-linear. So far so good.

But why is there not VAA14 and VAB14? Instead, I see a shared line VA14. I looked at nocash specs (https://problemkaputt.de/fullsnes.txt) and read this:

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47    SRAM   VA14       (sram address bus for upper/lower 8bit data)

Moreover, I found this text in SNES Developent Wifi (https://wiki.superfamicom.org/backgroun ... ress%20bus).

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note that in hardware, VRAM is set up such that odd bytes are in one RAM chip and even in another, and each RAM chip has a separate address bus

But I wonder if this description is wrong.

With a single VA14 line, the even bytes are in the lower (0-16KiB) part of a chip. And the odd bytes are in the upper part (16-32KiB) of a chip. If that was to be correct interpretation, then the single VA14 would make sense. Do I understand it correctly?

[UnDisbeliever]

When rendering mode 0-6 backgrounds and sprites the PPU treats VRAM as 16bit memory and the two VRAM address buses will hold the same value. The low-byte is stored in one VRAM chip and the high-byte is stored in the other VRAM chip.

The PPU will only use different values for the two VRAM address buses for the Mode 7 background. The low-VRAM chip holds the Mode 7 tilemap and the high-VRAM chip holds the Mode 7 tile-data. Since the Mode 7 tilemap (16KiB) and tile-data (16KiB) both start at VRAM address 0, VRAM address bits 14 and 15 will always be 0.

Finally, the PPU has a different access pattern for the VRAM registers. When the S-CPU reads or writes to VRAM using the PPU registers, the PPU treats VRAM as two separate 8bit memory chips with a shared auto-incrementing address bus (with optional remapping). How the address bus is incremented (and mapped) is controlled by the VMAIN register. See Reading and writing PPU memory: VRAM on the wiki for more details. [EDIT2: Not correct, see below]

Since VRAM address bits 14 and 15 will always contain the same values they can be shared across the two VRAM chips.

Since there is only 64KiB of VRAM on the SNES, VRAM address bit 15 (VA15) is not connected to the VRAM chips.


EDIT: I do not know if VAA# and VAB# contain the same values when reading/writing VRAM using VMDATAL, VMDATAH, VMDATAHREAD or VMDATALREAD registers

[UnDisbeliever]

I made a mistake above regarding PPU's VRAM registers. I forgot about the VRAM read latch.

According to ares code, when the S-CPU is reading VRAM using the PPU registers (during VBlank/Force-Blank) the PPU will do a 16bit VRAM read to the vram latch when:

• VMADDL or VMADDH (VRAM word address registers) are written to.
• VMDATALREAD is read and VMAIN.bit7 is 0 (before the internal VRAM address increments).
• VMDATAHREAD is read and VMAIN.bit7 is 1 (before the internal VRAM address increments).

I personally believe that writing to the VRAM with the VMDATAL & VMDATAH registers is done with 8bit writes because there are two VRAM write control lines (labelled /VAWR and /VBWR in the Jonathon W. Donaldson schematic). However, I've searched this forum for any evidence to confirm this and I cannot find it. Maybe I'm misremembering something...

I did find two posts on the VRAM bus activity for Modes 0-6 (link1, link2), but nothing for the VRAM registers.

[lidnariq]

The PPU only has control over the VRAM /WE signal - /CE and /OE are always grounded. As such, it's always continuously reading, except at the exact moments it's writing.

[fabiensanglard]

@UnDisbeliever, you king. Thank you so much! It makes perfect sense now!