Sakigake!! Otoko Juku - Shippuu Ichi Gou Sei PCB

[zxbdragon]

Sakigake!! Otoko Juku - Shippuu Ichi Gou Sei

CTC-01
3920

[aquasnake]

科統實業股份有限公司

Co Tung Co.

Maybe another variant of mapper #417, and with an M2 based countdown countor

[krzysiobal]

I would guess for something like that, though I am not sure about the 74138 input bits (A/B/C).

[aquasnake]

https://forums.nesdev.org/viewtopic.php?f=28&t=12288


similar to this board: Mapper #??? - pirate Nekketsu Monogatari

[zxbdragon]

https://forums.nesdev.org/viewtopic.php?f=28&t=12288


similar to this board: Mapper #??? - pirate Nekketsu Monogatari

this board not like pirate Nekketsu Monogatari,


Sakigake!! Otoko Juku - Shippuu Ichi Gou Sei (J) [p1]
PCB:3920
Map(0x8EF0U, CHR_SWAP_1K_0);
Map(0x8EF1U, CHR_SWAP_1K_1);
Map(0x8EF2U, CHR_SWAP_1K_2);
Map(0x8EF3U, CHR_SWAP_1K_3);
Map(0x8EF4U, CHR_SWAP_1K_4);
Map(0x8EF5U, CHR_SWAP_1K_5);
Map(0x8EF6U, CHR_SWAP_1K_6);
Map(0x8EF7U, CHR_SWAP_1K_7);
Map(0x8EF8U, PRG_SWAP_16K_0);
Map(0x8EF9U, NMT_SWAP_VH01);
//Map(0x8EFAU, 0x8EFFU, NOP_POKE);??

Map(0x8EE0U, &Btl3920::Poke_F000); IRQ enable or latch?
Map(0x8EFCU, &Btl3920::Poke_F000); IRQ disable?

Mapper 159 ,IRQ Change

[krzysiobal]

https://forums.nesdev.org/viewtopic.php?f=28&t=12288


similar to this board: Mapper #??? - pirate Nekketsu Monogatari

this board not like pirate Nekketsu Monogatari,


Sakigake!! Otoko Juku - Shippuu Ichi Gou Sei (J) [p1]
PCB:3920
Map(0x8EF0U, CHR_SWAP_1K_0);
Map(0x8EF1U, CHR_SWAP_1K_1);
Map(0x8EF2U, CHR_SWAP_1K_2);
Map(0x8EF3U, CHR_SWAP_1K_3);
Map(0x8EF4U, CHR_SWAP_1K_4);
Map(0x8EF5U, CHR_SWAP_1K_5);
Map(0x8EF6U, CHR_SWAP_1K_6);
Map(0x8EF7U, CHR_SWAP_1K_7);
Map(0x8EF8U, PRG_SWAP_16K_0);
Map(0x8EF9U, NMT_SWAP_VH01);
//Map(0x8EFAU, 0x8EFFU, NOP_POKE);??

Map(0x8EE0U, &Btl3920::Poke_F000); IRQ enable or latch?
Map(0x8EFCU, &Btl3920::Poke_F000); IRQ disable?

Mapper 159 ,IRQ Change

If there is something similar, it is rather this Dragon Ball:
http://raspberrypi/carts/?action=view&id=94

But I doubt your cartridge uses the same addressess for all regsiters like original mapper 16 rom.
One 74138 cannot decode everything over the same addresses. Dragon Ball required 74139+74138.
There need to be 4 byte gap between CHR1 $000-$0fff, CHR2 $1000-$1fff, PRG, IRQ and Mirroring regsiter.

Also mirroring seem to be switched only between H and 1ScA.

[aquasnake]

According to the circuit diagram, I wrote the verilog logic roughly, maybe there are errors.

In fact, it is very similar to pirate Nekketsu Monogatari

prg mode is 16K+fixed 16K mode, so the remaining 3 prg bank registers are ignored

mirroring modes are different also

The IRQ counter takes 2048 as the prescalar, and then sets the 4-bit counter, so it can be assumed that only the high bits need to be set: [14:11]

Code: Select all

				// Mapper #??? - pirate Sakigake!! Otoko Juku
				begin
					irq_cpu_cd_enabled = 1;
					casez (cpu_addr_in[4:0]) // casez (cpu_addr_in[6:4], cpu_addr_in[1:0]) ???
						5'b000??: prg_bank_a[4:1] = cpu_data_in[3:0];
						5'b10000: chr_bank_a = cpu_data_in;
						5'b10001: chr_bank_b = cpu_data_in;
						5'b10010: chr_bank_c = cpu_data_in;
						5'b10011: chr_bank_d = cpu_data_in;
						5'b10100: chr_bank_e = cpu_data_in;
						5'b10101: chr_bank_f = cpu_data_in;
						5'b10110: chr_bank_g = cpu_data_in;
						5'b10111: chr_bank_h = cpu_data_in;
						5'b110??: mirroring[1:0] = {cpu_data_in[0], 1'b1};
						5'b111??: begin
							irq_cpu_control[0] = cpu_data_in[0]; // IRQ enable
							irq_cpu_counter[14:11] = cpu_data_in[7:4]; // IRQ reload
							irq_cpu_counter[10:0] = 0;
							irq_cpu_out = 0; // IRQ ack
						end
					endcase
				end

Code: Select all

				// Mapper #??? - pirate Nekketsu Monogatari
				begin
					irq_cpu_cu_enabled = 1;
					casez (cpu_addr_in[6:4], cpu_addr_in[1:0])
						5'b00000: prg_bank_a[4:0] = cpu_data_in[4:0];
						5'b00001: prg_bank_c[4:0] = cpu_data_in[4:0];
						5'b00010: prg_bank_b[4:0] = cpu_data_in[4:0];
						5'b00100: chr_bank_a = cpu_data_in;
						5'b00101: chr_bank_b = cpu_data_in;
						5'b00110: chr_bank_c = cpu_data_in;
						5'b00111: chr_bank_d = cpu_data_in;
						5'b01000: chr_bank_e = cpu_data_in;
						5'b01001: chr_bank_f = cpu_data_in;
						5'b01010: chr_bank_g = cpu_data_in;
						5'b01011: chr_bank_h = cpu_data_in;
						5'b011??: begin
							irq_cpu_control[0] = cpu_data_in[0]; // IRQ enable
							irq_cpu_out = 0; // IRQ ack
						end
						5'b100??: irq_cpu_counter[7:0] = cpu_data_in; // IRQ reload low
						5'b101??: irq_cpu_counter[15:8] = cpu_data_in; // IRQ reload high
					endcase
				end

[aquasnake]

The TTL implemented mapper #16 looks like this:




Here is the mapper #417 pirate cart, which is more like?

The pirates are very smart, they like to use the cd4020 to simplify the IRQ counter design, the game's IRQ timer is coarse, and does not need to be accurate to each M2 cycle, and the fixed value of the exponent of 2 is used for the prescaler, which can save a few 74ls191s

[zxbdragon]

The TTL implemented mapper #16 looks like this:




Here is the mapper #417 pirate cart, which is more like?

The pirates are very smart, they like to use the cd4020 to simplify the IRQ counter design, the game's IRQ timer is coarse, and does not need to be accurate to each M2 cycle, and the fixed value of the exponent of 2 is used for the prescaler, which can save a few 74ls191s

dragon ball 3 rom data is original

[zxbdragon]

According to the circuit diagram, I wrote the verilog logic roughly, maybe there are errors.

In fact, it is very similar to pirate Nekketsu Monogatari

prg mode is 16K+fixed 16K mode, so the remaining 3 prg bank registers are ignored

mirroring modes are different also

The IRQ counter takes 2048 as the prescalar, and then sets the 4-bit counter, so it can be assumed that only the high bits need to be set: [14:11]

Code: Select all

				// Mapper #??? - pirate Sakigake!! Otoko Juku
				begin
					irq_cpu_cd_enabled = 1;
					casez (cpu_addr_in[4:0]) // casez (cpu_addr_in[6:4], cpu_addr_in[1:0]) ???
						5'b000??: prg_bank_a[4:1] = cpu_data_in[3:0];
						5'b10000: chr_bank_a = cpu_data_in;
						5'b10001: chr_bank_b = cpu_data_in;
						5'b10010: chr_bank_c = cpu_data_in;
						5'b10011: chr_bank_d = cpu_data_in;
						5'b10100: chr_bank_e = cpu_data_in;
						5'b10101: chr_bank_f = cpu_data_in;
						5'b10110: chr_bank_g = cpu_data_in;
						5'b10111: chr_bank_h = cpu_data_in;
						5'b110??: mirroring[1:0] = {cpu_data_in[0], 1'b1};
						5'b111??: begin
							irq_cpu_control[0] = cpu_data_in[0]; // IRQ enable
							irq_cpu_counter[14:11] = cpu_data_in[7:4]; // IRQ reload
							irq_cpu_counter[10:0] = 0;
							irq_cpu_out = 0; // IRQ ack
						end
					endcase
				end

Code: Select all

				// Mapper #??? - pirate Nekketsu Monogatari
				begin
					irq_cpu_cu_enabled = 1;
					casez (cpu_addr_in[6:4], cpu_addr_in[1:0])
						5'b00000: prg_bank_a[4:0] = cpu_data_in[4:0];
						5'b00001: prg_bank_c[4:0] = cpu_data_in[4:0];
						5'b00010: prg_bank_b[4:0] = cpu_data_in[4:0];
						5'b00100: chr_bank_a = cpu_data_in;
						5'b00101: chr_bank_b = cpu_data_in;
						5'b00110: chr_bank_c = cpu_data_in;
						5'b00111: chr_bank_d = cpu_data_in;
						5'b01000: chr_bank_e = cpu_data_in;
						5'b01001: chr_bank_f = cpu_data_in;
						5'b01010: chr_bank_g = cpu_data_in;
						5'b01011: chr_bank_h = cpu_data_in;
						5'b011??: begin
							irq_cpu_control[0] = cpu_data_in[0]; // IRQ enable
							irq_cpu_out = 0; // IRQ ack
						end
						5'b100??: irq_cpu_counter[7:0] = cpu_data_in; // IRQ reload low
						5'b101??: irq_cpu_counter[15:8] = cpu_data_in; // IRQ reload high
					endcase
				end

It seems incorrect; the simulation based on your description was not successful.

Mod note: The discussion continues in Chinese in this topic