Using Dendy CPU in NTSC console

[krzysiobal]

Using Dendy CPU in NTSC console

The cost of building NTSC console in significantly larger when compared to Dendy.
Thaat's because NTSC CPU/PPU costs about 13$/pc in comparision to about 2$/pc for Dendy chips (aliexpress).

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      | CPU       PPU
------+-----------------
NTSC  | UA6527  UA6528
Dendy | UA6527P UA6538

And you still cannot be 100% sure what you are buying until you test it, just like those faked UA6527 which turned out to be in fact UA6527P. Clocking with 21.477272 MHz and measuring M2 (1.43 MHz) proved it has internal divider 15 (21.477272/15=1.43) rather than expected 12 (21.4777272/12=1.78MHz)


When you put together NTSC PPU with Dendy CPU, most of the games wont work properly as the PPU/CPU ratio will stop being 3).


Since Dendy and NTSC CPUs are basically identical and the only difference is internal clock divider (15 or 16 for Dendy and 12 for NTSC), I thought of adding small logic chip that for each 12 input clocks will output 16 cloc cycles, so the resulting M2 frequency would be the same.

Dendy CPUs before mid 1990 have divider=16 and after mid 1990 have divider=15.


A quick calculation:
1 clock @ 21.7Mhz = 46,56ns
12 clocks @ 21.7Mhz = 558,72ns
So 16 clocks at 558.72ns would take 34,92ns each, which is just a little slower than 33.33MHz

CPLD is clocked with external 100MHz resonator, its frequency is divided to 33.33Mhz and synced with the 21.7Mhz clock. So you get 33.33MHz clock and a little of silence so it is kept in phase with 21.7Mhz.
As you can see, the resulting M2 produced by CPU is 1.78MHz, identical as if the CPU got 12 divider.



All NTSC games work just as this would be NTSC CPU.


Console doesn't have the original transistor clock generator. Its peak to peak amplitude is too low for CPL. What I used instead is the 74HCU04 gate:


The same technique can be used when trying to use old Dendy CPUs (16clk div) as new Dendy CPUs (15clk div) - just generate 15 cycles

[borishim]

Nice! For what it worth, I also took a similar approach using a clock multiplier chip (ICS501) and a flip-flop (74HC74)
An ICS501 chip can multiply a clock by 5x. So I created a 1.25x clock multiplier (divide the original clock by 4 with 74HC74 and multiply the divided clock by 5 with ICS501) With this, you can also achieve an overall divisor of 12 (1.25/15 = 1/12). I confirmed that this trick works very well.
I hope to find a way to utilize PAL ppu for NTSC video, but I haven't come up with any idea yet... (perhaps there's none)

[forple]

You can't use PAL PPUs for NTSC video unless you have a video converter, and even then it'd have to be a limited selection of PPUs, specifically the ones capable of doing PAL60 video output, if you want to keep the proper 60Hz timing.

I find the rest of this thread interesting, but the catch is that the 6527-series CPU isn't a very good clone to begin with (namely in bad duty cycles) so the only alternative I can think of is for the WDL UM03 or TA-03NP chips which use the same divisor but applied to a die mask clone of an official 2A03, so things like the APU remain properly functional. But I do agree in that it's likely much more convenient given the relative cheapness of clone chipsets compared to the official ones which are rapidly increasing in price as time goes on (even moreso for certain official chipsets...)

[krzysiobal]

Oh, never heard about ICS501, thanks for suggestion.

When creating multiregion console (Dendy+NTSC), this approach simplifies the designbecause only 3 processors need to be used instead of 4.
And what is more important, because there is only one CPU, Denty/'NTSC mode can be switched even on the fly without breaking the game.

Wrong APU duty cycle can be easily fixed in the fly by replacing writes to $4000/$4004 with fixed values "on the fly" (if there's already a small CPLD that generates the proper clock with only 4 pins used (clk_in, clk_out, clk_100mhz, clk_fix_enabled) why not use it also for the APU purpose.

Turning Dendy PPU into NTSC PPU also is possible in my opinion. First, you need to overclock it with 60/50 frequency.
Next step is to sample the EXT0..EXT3 signals to get color pixel values. Mising EXT4 can be recovered from its video signal. To make it easier:
* replace all colors in the palette with indices 0..3 to white
* replace colors with index 4 to black
Now to distinguish 0..15 from 16..31 just a simple voltage comparator would be needed.

And then add an externail circuitry that encodes the raw pixel to NTSC signal. There are surely special chips for that purpose.

[borishim]

You can't use PAL PPUs for NTSC video unless you have a video converter, and even then it'd have to be a limited selection of PPUs, specifically the ones capable of doing PAL60 video output, if you want to keep the proper 60Hz timing.

Personally I 100% agree with you. I'm just hesitant to say something is impossible because to prove something is impossible is much harder than proving something is possible

I find the rest of this thread interesting, but the catch is that the 6527-series CPU isn't a very good clone to begin with (namely in bad duty cycles) so the only alternative I can think of is for the WDL UM03 or TA-03NP chips which use the same divisor but applied to a die mask clone of an official 2A03, so things like the APU remain properly functional. But I do agree in that it's likely much more convenient given the relative cheapness of clone chipsets compared to the official ones which are rapidly increasing in price as time goes on (even moreso for certain official chipsets...)

I think that it depends- some of us (especially out of US/JP) have their childhood memories built on top of bad duty cycles When I restore famiclones, I usually use UMC chips. Of course, I use original chips to restore original famicoms and NES consoles. I also believe that TA-03NP has a divisor of 12 (and they are a bit harder to source than UMC chips.) Perhaps you wanted to mention TA-03NP1?