SNES S-CPU Data bus direction

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leonllrmc
Posts: 2
Joined: Tue Feb 04, 2025 3:55 am

SNES S-CPU Data bus direction

Post by leonllrmc »

Hey,

As part of a project to replace the S-CPU with a FPGA,
I'm trying to determine the direction of the data bus (if its currently writing or reading), since this is needed to set the direction of a level shifter.

Researching the S-CPU logic schematic, I've came up with the following expression: (I'm using snestang IP as a base)

Code: Select all

assign D_DIR = (DMA_ACTIVE && CPU_RD && ~DMA_B_WR && ~HDMA_A_RD && ~P65_EN) || (~DMA_ACTIVE && ((~CPU_WR && SYSCLK && ~P65_EN) || (CPU_RD && ~P65_EN)));
The DIR is supposed to be 1 when writing, else 0

The expression from the logic schematic on which it's based is the following:
DATA Bus is DOUT from CPU when one of the following conditions are met:
- DMA is on and CPU_REG_RD = '1' and DMA_B->A = '0' and HDMA_TABLE_RD = '0' and ~{RDY}= '0'
- DMA is off and ((R~{W}= '0' and SYSCLK = '1' and ~{RDY}= '0') or (CPU_REG_RD = '1' and ~{RDY}= '1'))
ACLK is used instead of SYSCLK but it is an inverted version of it.
DATA Bus is DIN to CPU when one of the following conditions are met:
- DMA is on and (CPU_REG_RD = '0' or DMA_B->A = '1' or HDMA_TABLE_RD = '1' or ~{RDY}= '1')
- DMA is off and R~{W}= '1' and ~{RDY}= '0' and CPU_REG_RD = '0'

Thanks in advance for anyone who helps !
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