NES Pro Action Replay - DIY

[Modman]

Greetings All,

Here are the KiCad files, dumped PALCE JEDEC, and dumped PRG and CHR binaries for the NES Pro Action Replay. Happy making!

The manual is too large to attach here, but this is a link to it: https://github.com/RWeick/NES-Pro-Actio ... Manual.pdf

[Memblers]

Very cool!

I stumbled into one of these years ago on ebay, I think it weirdly has a 3-layer PCB. I was disappointed that it wouldn't work on my NTSC NES, grey screen only. When I did get a PAL NES later, it seemed to work in that I could see the interface, at least. None of my TVs could handle the PAL signal, as it turned out (no colors + rolling).

If it's the same software, worth noting that for me that it might just hang on an NTSC system. Looking in an emulator, the code was doing PAL-timed stuff with the PPU. It should work if the software was modified though, if someone wants to do that. If I have the time eventually, I might try making one into a blank cart writer, like I did with the Game Genie.

[Modman]

Oh yes, the original board was 3 layers. I found that it wasn’t necessary though, and that everything could fit comfortably on 2 layers. I’ve attached the board scans I made of the original.

It would be amazing if someone wanted to make an ntsc compatible rom! That is beyond my skill set or I would happily do it myself. But, yes, this is the original PAL software that I’ve shared here, so it is unlikely to just work as is in an ntsc system

[krzysiobal]

Wasn't the GAL read-protected at all or did you just bute force its outputs?
I was going to read it but never found motivation.
I think it's better to make repro using some modern and more popular CPLD chips.

[Modman]

Wasn't the GAL read-protected at all or did you just bute force its outputs?
I was going to read it but never found motivation.
I think it's better to make repro using some modern and more popular CPLD chips.

Yes it is read protected. I found a few years ago that a pld programmer called the RunFei 3148 had built in capability to defeat the read protection on certain PALs and GALs, including the one used in this device. So that is how I achieve an actual dump rather than a brute forced solution

And yes, I’ve decoded the jedec to standard logic so it would be easy to implement it on a more modern pld/fpga if anyone wanted to

[TakuikaNinja]

It should be noted that the PAR has different revisions leading up to v1.2 (the one dumped here). TCRF claims that v1.2 has a secret screen accessed by holding select while resetting.

[marvinsaint]

Wasn't the GAL read-protected at all or did you just bute force its outputs?
I was going to read it but never found motivation.
I think it's better to make repro using some modern and more popular CPLD chips.

Yes it is read protected. I found a few years ago that a pld programmer called the RunFei 3148 had built in capability to defeat the read protection on certain PALs and GALs, including the one used in this device. So that is how I achieve an actual dump rather than a brute forced solution

And yes, I’ve decoded the jedec to standard logic so it would be easy to implement it on a more modern pld/fpga if anyone wanted to

Hello friend, im able to make a schematic capture on 3 layers pcb

But could you confirm If PAL extract process was sucessfull ?
Do you have burned and tested in your original pcb ??

[marvinsaint]

Greetings All,

Here are the KiCad files, dumped PALCE JEDEC, and dumped PRG and CHR binaries for the NES Pro Action Replay. Happy making!

Could you send assembled pcb pictures?

[NARN]

Greetings All,

Here are the KiCad files, dumped PALCE JEDEC, and dumped PRG and CHR binaries for the NES Pro Action Replay. Happy making!

Will it work on Famicom if I make a 60 pin board?

[Modman]

Wasn't the GAL read-protected at all or did you just bute force its outputs?
I was going to read it but never found motivation.
I think it's better to make repro using some modern and more popular CPLD chips.

Yes it is read protected. I found a few years ago that a pld programmer called the RunFei 3148 had built in capability to defeat the read protection on certain PALs and GALs, including the one used in this device. So that is how I achieve an actual dump rather than a brute forced solution

And yes, I’ve decoded the jedec to standard logic so it would be easy to implement it on a more modern pld/fpga if anyone wanted to

Hello friend, im able to make a schematic capture on 3 layers pcb

But could you confirm If PAL extract process was sucessfull ?
Do you have burned and tested in your original pcb ??

Hi, yes I've burned the PAL and confirmed the extract process was successful. The PAL equations from the extracted chip are as follows:

/SRAM.CS1.OE = ROMSEL.Sys and Addr: 0x5000 - 0x5FFF

/CPU_FF_CLK = /ROMSEL.Sys and PAR_CHRROM_EN and Addr: 0x7FFA

/PPU_FF_CLK = /ROMSEL.Sys and Addr: 0x7FF8

Many thanks to Lidnariq for reasoning that the addresses for the flip flop clocks are actually 0xFFFA and 0xFFF8 due to ROMSEL being low when A15 is high.

I've attached a photo of my current state as I'm awaiting a few components necessary to make new ones, but I've obviously reassembled the original and will be assembling a few new ones most of the way very shortly.

This is the DPDT switch I've found for it, which closely matches the original: https://www.sameskydevices.com/product/ ... 569-4a-n-d

[Modman]

Greetings All,

Here are the KiCad files, dumped PALCE JEDEC, and dumped PRG and CHR binaries for the NES Pro Action Replay. Happy making!

Will it work on Famicom if I make a 60 pin board?

I don't have the experience necessary to give you an answer on this, perhaps someone else here can say for sure

[marvinsaint]

Yes it is read protected. I found a few years ago that a pld programmer called the RunFei 3148 had built in capability to defeat the read protection on certain PALs and GALs, including the one used in this device. So that is how I achieve an actual dump rather than a brute forced solution

And yes, I’ve decoded the jedec to standard logic so it would be easy to implement it on a more modern pld/fpga if anyone wanted to

Hello friend, im able to make a schematic capture on 3 layers pcb

But could you confirm If PAL extract process was sucessfull ?
Do you have burned and tested in your original pcb ??

Hi, yes I've burned the PAL and confirmed the extract process was successful. The PAL equations from the extracted chip are as follows:

/SRAM.CS1.OE = ROMSEL.Sys and Addr: 0x5000 - 0x5FFF

/CPU_FF_CLK = /ROMSEL.Sys and PAR_CHRROM_EN and Addr: 0x7FFA

/PPU_FF_CLK = /ROMSEL.Sys and Addr: 0x7FF8

Many thanks to Lidnariq for reasoning that the addresses for the flip flop clocks are actually 0xFFFA and 0xFFF8 due to ROMSEL being low when A15 is high.

I've attached a photo of my current state as I'm awaiting a few components necessary to make new ones, but I've obviously reassembled the original and will be assembling a few new ones most of the way very shortly.

This is the DPDT switch I've found for it, which closely matches the original: https://www.sameskydevices.com/product/ ... 569-4a-n-d

About pcb, are a normal two layers pcb or a three layers ?
Your project até working? I can use your files.??

[Modman]

Hello friend, im able to make a schematic capture on 3 layers pcb

But could you confirm If PAL extract process was sucessfull ?
Do you have burned and tested in your original pcb ??

Hi, yes I've burned the PAL and confirmed the extract process was successful. The PAL equations from the extracted chip are as follows:

/SRAM.CS1.OE = ROMSEL.Sys and Addr: 0x5000 - 0x5FFF

/CPU_FF_CLK = /ROMSEL.Sys and PAR_CHRROM_EN and Addr: 0x7FFA

/PPU_FF_CLK = /ROMSEL.Sys and Addr: 0x7FF8

Many thanks to Lidnariq for reasoning that the addresses for the flip flop clocks are actually 0xFFFA and 0xFFF8 due to ROMSEL being low when A15 is high.

I've attached a photo of my current state as I'm awaiting a few components necessary to make new ones, but I've obviously reassembled the original and will be assembling a few new ones most of the way very shortly.

This is the DPDT switch I've found for it, which closely matches the original: https://www.sameskydevices.com/product/ ... 569-4a-n-d

About pcb, are a normal two layers pcb or a three layers ?
Your project até working? I can use your files.??

Yes, I have fully tested a board made entirely from new components, and it is working perfectly.

It may not display properly on an ntsc system

[marvinsaint]

Hi, yes I've burned the PAL and confirmed the extract process was successful. The PAL equations from the extracted chip are as follows:

/SRAM.CS1.OE = ROMSEL.Sys and Addr: 0x5000 - 0x5FFF

/CPU_FF_CLK = /ROMSEL.Sys and PAR_CHRROM_EN and Addr: 0x7FFA

/PPU_FF_CLK = /ROMSEL.Sys and Addr: 0x7FF8

Many thanks to Lidnariq for reasoning that the addresses for the flip flop clocks are actually 0xFFFA and 0xFFF8 due to ROMSEL being low when A15 is high.

I've attached a photo of my current state as I'm awaiting a few components necessary to make new ones, but I've obviously reassembled the original and will be assembling a few new ones most of the way very shortly.

This is the DPDT switch I've found for it, which closely matches the original: https://www.sameskydevices.com/product/ ... 569-4a-n-d

About pcb, are a normal two layers pcb or a three layers ?
Your project até working? I can use your files.??

Yes, I have fully tested a board made entirely from new components, and it is working perfectly.

It may not display properly on an ntsc system

Nice i Will build one for me .Thanks.

Now lets expect someone modfiy The ROM for NTSC System.