Quest of Ki - cartridge with interesting NTC1024 chip

[krzysiobal]

I got photos of interesting cartridge with "Quest of Ki" game (mapper 206, MMC3 predecessor).
Never heard about NTC1024 chip before so I first thought it is some kind of mapper 206 clone, like AX-24G/NTDEC8701. But it wasnt the case as those chips have GND at pin 12, while this subjected NTC1024 has it at pin 14. Also the reason for presence of 74153 mux was unclear.

After diving more into the PCB I realised this mux
1) adds PRG-/CE which this mapper chip probably does not have
2) controls CHR-A10 between NTC-CHR-A10 (when PPU-A12 = 1) and PPU-A10 (when PPU-A12 = 0) which results in a MMC3-like CHR banking (2k+2k+1k+1k+1k+1k).

Code: Select all

+-----------+-----------+-----+-----+-----+-----+
|   $0000   |   $0800   |$1000|$1400|$1800|$1c00|
+-----------+-----------+-----+-----+-----+-----+

this means NTC1024 natively outputs 8x1kb CHR banks rather than 2k+2k+1k+1k+1k+1k.

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+-----+-----+-----+-----+-----+-----+-----+-----+
|$0000|$0400|$0800|$0c00|$1000|$1400|$1800|$1c00|
+-----+-----+-----+-----+-----+-----+-----+-----+

which would suggest is could be potentially used as VRC2/4 clone

Lots of jumpers make this board to be flexible for use either with 128kB PRG-ROM or 64kb+64kB EPROM.
And mirroring is also jumper-controlled.

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               .-----v----.
     CPU D2 -> | 01    28 | ?? VCC
     CPU D1 -> | 02    27 | <- CPU D3
     CPU D0 -> | 03    26 | <- CPU D4
     CPU M2 -> | 04    25 | <- CPU D5
CPU /ROMSEL -> | 05    24 | <- PPU A11
     CPU A0 -> | 06    23 | <- PPU A12
    CPU R/W -> | 07    22 | <- PPU A10
    CHR A10 <- | 08    21 | -> CHR A13
    CHR A11 <- | 09    20 | -> CHR A14
    CHR A12 <- | 10    19 | -> CHR A15
    CHR A13 <- | 11    18 | <- CPU A14
    PRG A13 <- | 12    17 | -> PRG A17
    PRG A14 <- | 13    16 | -> PRG A16
        GND ?? | 14    15 | -> PRG A15
               `----------`
                 NTC 1024

[lidnariq]

Does the data in the ROMs match the commercial release? Or is there a mapper hack?

MMC3/Namco 108 doesn't have enough indirect addresses (R0,1 are the two 2KB banks; R2-5 the four 1KB banks) so I'm not clear how the multiplexer could change that. Did they screw up the ASIC design and the two 2KB banks just emit the same 6-bit value regardless of PPU A10?

[krzysiobal]

Does the data in the ROMs match the commercial release? Or is there a mapper hack?

MMC3/Namco 108 doesn't have enough indirect addresses (R0,1 are the two 2KB banks; R2-5 the four 1KB banks) so I'm not clear how the multiplexer could change that. Did they screw up the ASIC design and the two 2KB banks just emit the same 6-bit value regardless of PPU A10?

Finally got that PCB for testing.
Yeah, ROM is byte-to-byte identical with commercial release.
CHR banking of this chip instead of expected

Code: Select all

+--------+--------+--------+--------+--------+--------+--------+--------+
| $0000  | $0800  | $1000  | $1400  | $1000  | $1400  | $1800  | $1c00  |
+--------+--------+--------+--------+--------+--------+--------+--------+
| R0 & ~1| R0 | 1 | R1& ~1 | R1 | 1 |   R2   |   R3   |   R4   |   R5   |
+--------+--------+--------+--------+--------+--------+--------+--------+

works like

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+--------+--------+--------+--------+--------+--------+--------+--------+
| $0000  | $0400  | $0800  | $0c00  | $1000  | $1400  | $1800  | $1c00  |
+--------+--------+--------+--------+--------+--------+--------+--------+
| R0     | R0     | R1     | R1     |   R2   |   R3   |   R4   |   R5   |
+--------+--------+--------+--------+--------+--------+--------+--------+

Also, when writing to $8000/$8001, CPU A13 and CPU A14 are ignored, that is:
* writing to $8000 is the same as to $a000, $c000, $e000
* writing to $8001 is the same as to $a001, $c001, $e001

I dont know if that is how commercial #206 works.

[lidnariq]

Namco 108 ignores writes to $A000 and up. That might be how they worked around a timing hazard between executing from $8000-$9FFF and accessing zero page.