Discrete mapper #019

[Jerry]

Hello, I got a card, which looks like mapper #019, but there is something wrong with the card. The boot is short-circuited, and the 16V8 is very hot. I suspect that it is broken. When I remove the 16V8, the short circuit does not exist. Are there any programming experts in this field? I posted the picture of the card.

[Jerry]

I removed the chip.

[Jerry]

4E 45 53 1A 10 20 32 10 00 00 00 00 00 00 00 00

I extracted the contents of the chip, and it runs well in the simulator.

[lidnariq]

This is a version of the Chinese game "San Guo Zhi 2", although the changes are profound enough that I don't know which came first.

[NewRisingSun]

Have you got a cartridge label picture that you would kindly share as well?

[krzysiobal]

Looking and the thin traces, gold plating, good quality o soldermask and descriptions underneath chips (especially AM27C040) I would bet this is some modern reproduction.

Interesting difference in title screen and scanline counter jitter in original version, not happening in yours:

title.PNG

Hello, I got a card, which looks like mapper #019, but there is something wrong with the card. The boot is short-circuited, and the 16V8 is very hot. I suspect that it is broken. When I remove the 16V8, the short circuit does not exist. Are there any programming experts in this field? I posted the picture of the card.

Where is the short-circuit? Between GND and VCC?


Looks almost like that:
http://krzysiobal.com/carts/?action=view&id=386

but yours is almost 100% compatible with mapper 019:
* no exp sound
* bits $e000.7, $e000.6, $e000.5 does not exist
* bits $e800.7, $e800.6, $e800.5 does not exist
* bits $f000.7, $f000.6, $f000.5 does not exist
* reg $f800 does not exists at all
* only writing at $5800-$5fff acknowledges pending irq

Code: Select all

              GAL16:
            .---v---.
M2_PIN01 -> |01   20| -- VCC
 CPU_A11 -> |02   19| -> CNTL_nWR
 CPU_A12 -> |03   18| -> CNTH_nWR
 CPU_A13 -> |04   17| -> WRAM_nCS
 CPU_A14 -> |05   16| -> CPU_A14_AND_A13
CPU_nRMS -> |06   15| -> CHR0_nGR
 CPU_RnW -> |07   14| -> CHR1_nGR
 PPU_A12 -> |08   13| -> CHR2_nGR
 PPU_A13 -> |09   12| -> CNT_CLK
     GND -- |10   11| <- M2_PIN11
            '-------'

I would assume the following GAL equations:

Code: Select all

/WRAM_nCS       = CPU_A14 * CPU_A13 * M2_PIN11 * CPU_nRMS
CPU_A14_AND_A13 = CPU_A14 * CPU_A13
/CNTL_nWR       = /CPU_RnW * M2_PIN11 * CPU_nRMS * CPU_A14 * /CPU_A13 * CPU_A12 * /CPU_A11
/CNTH_nWR       = /CPU_RnW * M2_PIN11 * CPU_nRMS * CPU_A14 * /CPU_A13 * CPU_A12 * CPU_A11
CNT_CLK         = /M2_PIN01
/CHR0_nGR       = /PPU_A13 * /PPU_A12
/CHR1_nGR       = /PPU_A13 *  PPU_A12
/CHR2_nGR       =  PPU_A13 * /PPU_A12

     fedcba9876543210
5000 0101000000000000
57ff 0101011111111111
5800 0101100000000000
5fff 0101111111111111
e7ff 1110011111111111

Open questions are:
* why M2 is feed both to pin 1 and 11 of pal
* why clock input of the four 74161s (CNT_CLK) are controlled by GAL, not directly tied to M2?
Maybe CNT_CLK is inverse of M2 or is it just buffered copy of M2?

Anyway, I attach my guessed. JED file for PAL.

proj.jed.zip

Registers with its corresponding bits:

Code: Select all

-IRQ REGISTERS-------------------------------------------------------------------------------------
[LLLLLLLL] @ $5000-$57ff (mask: $f800)         | Counter operation:
 ||||||||                                      | * write to $5000/$5800 to directly sets
 ++++++++-- irq counter low value              |   lower/upper byte of 16 bit counter
                                               | * if $5800.7 = 0, interrupt will be disabled
[HHHHHHHH] @ $5800-$5fff (mask: $f800)         |   (but counting still takes place)
 ||||||||                                      | * if counter overflows from $ffff to $0000,
 ++++++++-- irq counter high value             |   it is stopped and irq is triggered
 +--------- 0=interrupts disabled              | * writing anything to $5800-$5fff acknowledges
                                               |   pending irq and starts counter
-PRG REGISTERS-------------------------------------------------------------------------------------
[...PPPPP] @ $e000-$e7ff (mask: $f800)         | +-------+-------+-------+-------+
    |||||                                      | | $8000 | $a000 | $c000 | $e000 |
    +++++-- PRG bank at $8000                  | +-------+-------+-------+-------+
                                               |   $e000   $e800  $f000     -1
[...PPPPP] @ $e800-$efff (mask: $f800)         |   
    |||||                                      |
    +++++-- PRG bank at $a000                  |
                                               |
[...PPPPP] @ $f000-$f7ff (mask: $f800)         |
    |||||                                      |
    +++++-- PRG bank at $c000                  |
                                               |
[...PPPPP] @ $f800-$ffff (mask: $f800)         |
    |||||                                      |
    +++++-- latched in register but not used   |
-CHR REGISTERS-------------------------------------------------------------------------------------
[CCCCCCCC] @ $8000-$87ff (mask: $f800)         | +-------+-------+-------+-------+ 
[CCCCCCCC] @ $8800-$8fff (mask: $f800)         | | $0000 | $0400 | $0800 | $0c00 |
[CCCCCCCC] @ $9000-$97ff (mask: $f800)         | +-------+-------+-------+-------+
[CCCCCCCC] @ $9800-$9fff (mask: $f800)         |   $8000   $8800   $9000   $9800  
[CCCCCCCC] @ $a000-$a7ff (mask: $f800)         |   
[CCCCCCCC] @ $a800-$afff (mask: $f800)         | +-------+-------+-------+-------+
[CCCCCCCC] @ $b000-$b7ff (mask: $f800)         | | $1000 | $1400 | $1800 | $1c00 |
[CCCCCCCC] @ $b800-$bfff (mask: $f800)         | +-------+-------+-------+-------+
                                               |  $a000   $a800   $b000   $b800   
-MIRRORING REGISTERS-------------------------------------------------------------------------------
[.......M] @ $c000-$c7ff (mask: $f800)         | +-------+-------+-------+-------+
[.......M] @ $c800-$cfff (mask: $f800)         | | $2000 | $2400 | $2800 | $2c00 |
[.......M] @ $d000-$d7ff (mask: $f800)         | +-------+-------+-------+-------+
[.......M] @ $d800-$dfff (mask: $f800)         |  $c000.0 $c800.0 $d000.0 $d800.0
---------------------------------------------------------------------------------------------------

[Jerry]

This is a version of the Chinese game "San Guo Zhi 2", although the changes are profound enough that I don't know which came first.

Yes, from China.

[Jerry]

Have you got a cartridge label picture that you would kindly share as well?

I found a clear picture, I hope you can use it.

[Jerry]

Looking and the thin traces, gold plating, good quality o soldermask and descriptions underneath chips (especially AM27C040) I would bet this is some modern reproduction.

Interesting difference in title screen and scanline counter jitter in original version, not happening in yours:
title.PNG

Hello, I got a card, which looks like mapper #019, but there is something wrong with the card. The boot is short-circuited, and the 16V8 is very hot. I suspect that it is broken. When I remove the 16V8, the short circuit does not exist. Are there any programming experts in this field? I posted the picture of the card.

Where is the short-circuit? Between GND and VCC?


Looks almost like that:
http://krzysiobal.com/carts/?action=view&id=386

but yours is almost 100% compatible with mapper 019:
* no exp sound
* bits $e000.7, $e000.6, $e000.5 does not exist
* bits $e800.7, $e800.6, $e800.5 does not exist
* bits $f000.7, $f000.6, $f000.5 does not exist
* reg $f800 does not exists at all
* only writing at $5800-$5fff acknowledges pending irq

Code: Select all

              GAL16:
            .---v---.
M2_PIN01 -> |01   20| -- VCC
 CPU_A11 -> |02   19| -> CNTL_nWR
 CPU_A12 -> |03   18| -> CNTH_nWR
 CPU_A13 -> |04   17| -> WRAM_nCS
 CPU_A14 -> |05   16| -> CPU_A14_AND_A13
CPU_nRMS -> |06   15| -> CHR0_nGR
 CPU_RnW -> |07   14| -> CHR1_nGR
 PPU_A12 -> |08   13| -> CHR2_nGR
 PPU_A13 -> |09   12| -> CNT_CLK
     GND -- |10   11| <- M2_PIN11
            '-------'

I would assume the following GAL equations:

Code: Select all

/WRAM_nCS       = CPU_A14 * CPU_A13 * M2_PIN11 * CPU_nRMS
CPU_A14_AND_A13 = CPU_A14 * CPU_A13
/CNTL_nWR       = /CPU_RnW * M2_PIN11 * CPU_nRMS * CPU_A14 * /CPU_A13 * CPU_A12 * /CPU_A11
/CNTH_nWR       = /CPU_RnW * M2_PIN11 * CPU_nRMS * CPU_A14 * /CPU_A13 * CPU_A12 * CPU_A11
CNT_CLK         = /M2_PIN01
/CHR0_nGR       = /PPU_A13 * /PPU_A12
/CHR1_nGR       = /PPU_A13 *  PPU_A12
/CHR2_nGR       =  PPU_A13 * /PPU_A12

     fedcba9876543210
5000 0101000000000000
57ff 0101011111111111
5800 0101100000000000
5fff 0101111111111111
e7ff 1110011111111111

Open questions are:
* why M2 is feed both to pin 1 and 11 of pal
* why clock input of the four 74161s (CNT_CLK) are controlled by GAL, not directly tied to M2?
Maybe CNT_CLK is inverse of M2 or is it just buffered copy of M2?

Anyway, I attach my guessed. JED file for PAL.
proj.jed.zip

Registers with its corresponding bits:

Code: Select all

-IRQ REGISTERS-------------------------------------------------------------------------------------
[LLLLLLLL] @ $5000-$57ff (mask: $f800)         | Counter operation:
 ||||||||                                      | * write to $5000/$5800 to directly sets
 ++++++++-- irq counter low value              |   lower/upper byte of 16 bit counter
                                               | * if $5800.7 = 0, interrupt will be disabled
[HHHHHHHH] @ $5800-$5fff (mask: $f800)         |   (but counting still takes place)
 ||||||||                                      | * if counter overflows from $ffff to $0000,
 ++++++++-- irq counter high value             |   it is stopped and irq is triggered
 +--------- 0=interrupts disabled              | * writing anything to $5800-$5fff acknowledges
                                               |   pending irq and starts counter
-PRG REGISTERS-------------------------------------------------------------------------------------
[...PPPPP] @ $e000-$e7ff (mask: $f800)         | +-------+-------+-------+-------+
    |||||                                      | | $8000 | $a000 | $c000 | $e000 |
    +++++-- PRG bank at $8000                  | +-------+-------+-------+-------+
                                               |   $e000   $e800  $f000     -1
[...PPPPP] @ $e800-$efff (mask: $f800)         |   
    |||||                                      |
    +++++-- PRG bank at $a000                  |
                                               |
[...PPPPP] @ $f000-$f7ff (mask: $f800)         |
    |||||                                      |
    +++++-- PRG bank at $c000                  |
                                               |
[...PPPPP] @ $f800-$ffff (mask: $f800)         |
    |||||                                      |
    +++++-- latched in register but not used   |
-CHR REGISTERS-------------------------------------------------------------------------------------
[CCCCCCCC] @ $8000-$87ff (mask: $f800)         | +-------+-------+-------+-------+ 
[CCCCCCCC] @ $8800-$8fff (mask: $f800)         | | $0000 | $0400 | $0800 | $0c00 |
[CCCCCCCC] @ $9000-$97ff (mask: $f800)         | +-------+-------+-------+-------+
[CCCCCCCC] @ $9800-$9fff (mask: $f800)         |   $8000   $8800   $9000   $9800  
[CCCCCCCC] @ $a000-$a7ff (mask: $f800)         |   
[CCCCCCCC] @ $a800-$afff (mask: $f800)         | +-------+-------+-------+-------+
[CCCCCCCC] @ $b000-$b7ff (mask: $f800)         | | $1000 | $1400 | $1800 | $1c00 |
[CCCCCCCC] @ $b800-$bfff (mask: $f800)         | +-------+-------+-------+-------+
                                               |  $a000   $a800   $b000   $b800   
-MIRRORING REGISTERS-------------------------------------------------------------------------------
[.......M] @ $c000-$c7ff (mask: $f800)         | +-------+-------+-------+-------+
[.......M] @ $c800-$cfff (mask: $f800)         | | $2000 | $2400 | $2800 | $2c00 |
[.......M] @ $d000-$d7ff (mask: $f800)         | +-------+-------+-------+-------+
[.......M] @ $d800-$dfff (mask: $f800)         |  $c000.0 $c800.0 $d000.0 $d800.0
---------------------------------------------------------------------------------------------------

The temperature of 16V8 is very high. I suspect that there is something wrong with it. I downloaded your JED file and successfully ran it. No problems have been found for the time being. Thank you very much. You are a genius.

[Jerry]

Is it possible to add some chips to repair the sound part?

[stan423321]

If I understood correctly, the answer seems to be no. Sound generation is significantly more complex to implement in discrete parts than bank mapping. For some mappers a standalone sound generator chip could be substituted, but for N163 the design seems bespoke.

[krzysiobal]

Some time ago I was working on a repro cartridge for "Pacman CE (Championship Edition)" and "Mappy - 30th Anniversary Edition". Both games are amateur hack, ported to mapper #019. They use N163's audio extensively and they're completely silent if no N163 audio is emulated.
While N163 banking & IRQs might seem complex in discrete, they fit perfetly into small CPLD like EPM240:
5bits * 3 regs for PRG + 8bits * 12 regs for CHR + 16 bits for IRQ counter + some bits for adder is rougly 127 macrocells.

However, if you see the descriptipon of audio part:
https://www.nesdev.org/wiki/Namco_163_audio

there are 128 resiters * 8bits = 1024bits which is even too much for bigger CPLDs in that Max II altera family (like EPM570), though something like Xilinx XC3S50 should fit fine.
Since audio sample need to be generated after 15 CPU cycles (not instantly), You could theoreticaly store all audio registers in separate RAM and then use even small FPGA to generate it in many cycles:
* w[$80] = the 163's internal memory
* sample(x) = (w[x/2] >> ((x&1)*4)) & $0F
* phase = (w[$7D] << 16) + (w[$7B] << 8) + w[$79]
* freq = ((w[$7C] & $03) << 16) + (w[$7A] << 8) + w[$78]
* length = 256 - (w[$7C] & $FC)
* offset = w[$7E]
* volume = w[$7F] & $0F

I was trying to implement the above algorithm in small microcontroller like Atmega 8 and it took me 65 AVR CPU cycles to output one audio sample.
Because AVR can be clocked with up to 16 MHz crystal which is about 16 MHz / 1,77 MHz = 9 times faster than NES cpu, it would take about 7 NES cycles to output sample which would be within limits (not longer than 15).

All you would need is to trigger AVR when CPU writes to
$E000, $F800, $4800 and pass the CPU data someway.
This AVR could not only be used to generate audio but also for games that use some of the N163 audio registers as internal RAM storage but passing the data from AVR to CPU would probably require extra buffer so the AVR wont drive the CPU data bus after CPU cycle ends.

[Jerry]

Some time ago I was working on a repro cartridge for "Pacman CE (Championship Edition)" and "Mappy - 30th Anniversary Edition". Both games are amateur hack, ported to mapper #019. They use N163's audio extensively and they're completely silent if no N163 audio is emulated.
While N163 banking & IRQs might seem complex in discrete, they fit perfetly into small CPLD like EPM240:
5bits * 3 regs for PRG + 8bits * 12 regs for CHR + 16 bits for IRQ counter + some bits for adder is rougly 127 macrocells.

However, if you see the descriptipon of audio part:
https://www.nesdev.org/wiki/Namco_163_audio

there are 128 resiters * 8bits = 1024bits which is even too much for bigger CPLDs in that Max II altera family (like EPM570), though something like Xilinx XC3S50 should fit fine.
Since audio sample need to be generated after 15 CPU cycles (not instantly), You could theoreticaly store all audio registers in separate RAM and then use even small FPGA to generate it in many cycles:
* w[$80] = the 163's internal memory
* sample(x) = (w[x/2] >> ((x&1)*4)) & $0F
* phase = (w[$7D] << 16) + (w[$7B] << 8) + w[$79]
* freq = ((w[$7C] & $03) << 16) + (w[$7A] << 8) + w[$78]
* length = 256 - (w[$7C] & $FC)
* offset = w[$7E]
* volume = w[$7F] & $0F

I was trying to implement the above algorithm in small microcontroller like Atmega 8 and it took me 65 AVR CPU cycles to output one audio sample.
Because AVR can be clocked with up to 16 MHz crystal which is about 16 MHz / 1,77 MHz = 9 times faster than NES cpu, it would take about 7 NES cycles to output sample which would be within limits (not longer than 15).

All you would need is to trigger AVR when CPU writes to
$E000, $F800, $4800 and pass the CPU data someway.
This AVR could not only be used to generate audio but also for games that use some of the N163 audio registers as internal RAM storage but passing the data from AVR to CPU would probably require extra buffer so the AVR wont drive the CPU data bus after CPU cycle ends.

Unfortunately, I can't program CPLD, FPGA and other chips. I really appreciate your help.

[Ben Boldt]

Unfortunately, I can't program CPLD, FPGA and other chips. I really appreciate your help.

Sure you can. It is not very hard and it is not very expensive. What part of it is stopping you?

[Jerry]

Sorry, I know some simple logic circuits. I'm not a programmer.