Respectfully, could I get a second set of eyes on the data line gating of my enhancement cart

[spaceharrier]

For the enhancement cartridge I am working on, I am utilizing a dual core microcontroller (STM32H745 line) that has tightly coupled SRAM between the cores which, even with internal-access penalties between the microcontroller cores, should allow the lower power core to act as a bus arbitrator for read and write requests from the 5A22. The slower core should be fast enough to service this if I keep a tight, bare metal routine.

In the attachment is a design segment showing the 3.3 to 5 volt logic level translation. I would like to use the output enable signal of the logic level translator with proper signal gating to automatically tri state my cartridge data pins.

Before I go destroying my Super NES in breadboarding, I would appreciate a second set of eyes. (Ignore the componnent assigned by kicad, I am using HTC series components for testing. Also ignore the lack bidirectional data to handle writes, my microcontroller decodes the address to provide a limited set of 8 bit mailboxes.)