FPGA replacement for NES APU 2a03

[andkorzh]

A highly clock-accurate FPGA clone of the NES/Famicom 2A03(7) APU (pAPU), created on the basis of reverse engineering.
After successfully launching the project to replace the NES PPU, I decided to do a similar project for the APU. I wrote the audio channel modules in Verilog back in early 2022, but I spent a long time searching for a suitable 6502 core to integrate into the APU. Finally, I decided to write my own 6502 core, and after three months of troubleshooting, it was working successfully in the native 2A03 environment. Now I had to fix the audio channel errors to ensure everything worked properly. By the beginning of 2024, I had already fixed all the errors except for error # 19 APU Blarrg test and unofficial opcode 6502 AB (ATX).

The sound is output via two R2R DACs, but the board has the ability to output individual channels in PWM format and then mix them. For now, I've settled on the R2R DAC, as it provides better quality compared to the PWM.

The model is based on the Cyclone II EP2C5T144C8 and takes up approximately 34% of its capacity. The remaining space can allow you to create a standalone NSF player if anyone wishes.

2A03PROTO.jpg

2a03 report.PNG

Video on YouTube: https://www.youtube.com/watch?v=RvPh_PWV7ng

This is an open source project, you can find it in my GitHub repository. https://github.com/andkorzh/RP2A03-7-/tree/main