Adding SRAM to discrete mappers

[kyuusaku]

Someone else here claims that this decoding can be done with one or two 7400 chips, but I'm waiting for him to post detailed instructions here or on the wiki.

Is that person me? 1.5x 7400 is the best one can do. It's also almost possible to decode WRAM with a single 74138 or 74139, but you need an inverter for /ROMSEL.



Do you think this is enough instruction?

[tepples]

Thank you. Wikified.

[Bregalad]

Someone else here claims that this decoding can be done with one or two 7400 chips, but I'm waiting for him to post detailed instructions here or on the wiki.

Is that person me? 1.5x 7400 is the best one can do. It's also almost possible to decode WRAM with a single 74138 or 74139, but you need an inverter for /ROMSEL.

You can do SRAM decoding with one SINGLE 7408 chip :

AND A13, A14, /ROMSEL and PHI2 together (it shouldn't matter in which order) and feed the output to positive chip enable pin, ground the negative chip enable pin and connect /WE to R/W and /OE to ground and that should to it.

[kyuusaku]

I meant the best anyone can do with 7400 (to properly decode signals) Your way is a little sneaky using the /WE priority and decoding all signals at once, also using the 6264's positive CE which isn't on any other chip, but it's a good trick ;)

With the two 7400, you can use 32K RAM and the recovered /RD and /WR signals for anything (like stopping bus conflicts)

[tepples]

Ahh, I forgot about the positive CE. The propagation may not be nice either though, like 60ns to decode

Or we could use one side of a 7420 (dual 4-input NAND) or 7421 (dual 4-input AND) chip.


EDIT: fix part number

[kyuusaku]

Or we could use one side of a 7420 (dual 4-input NAND) or 7420 (dual 4-input AND) chip.

After thinking about it, the propagation should be fine. Maybe this discrete mapper tricks conversation should have it's own thread?

[Bregalad]

I meant the best anyone can do with 7400 (to properly decode signals) Your way is a little sneaky using the /WE priority and decoding all signals at once, also using the 6264's positive CE which isn't on any other chip, but it's a good trick

I don't know why you call any of it sneaky. It's written on official 6264 datesheet that whenever /WE is low, the /OE is bypassed, as all pins are input anyway. That's how SRAMs are wired on EVERY Nintendo made board that have them (all least every standard ones).

And positive CE is also present on 128 KB SRAMs, but lacks in 32 KB and 2 KB SRAMs. Also, the MMC1 only deals with positive CE only (unless more logic is added externally like in SOROM and SXROM) while MMC5 only deals with negative CE, I guess MMC3 deals with both (most certainly one is only used as security for power-up/down). I don't know about MMC4 and VRC mappers, tough.

With the two 7400, you can use 32K RAM and the recovered /RD and /WR signals for anything (like stopping bus conflicts with the two "wasted" NANDs)

True, but you also could with a single 7420. And I don't know what you are talking about bus conflicts. As long RAM is only enabled for $6000-$7ffff, there cannot be any bus conflicts, since nothing else is mapped here.

[kyuusaku]

I don't know why you call any of it sneaky.

Tricky, because it doesn't have allow any setup times (so it's not suitable for slow memory or DRAM etc) and because of the /WE priority which is clever but isn't standard practice.

It's written on official 6264 datesheet that whenever /WE is low, the /OE is bypassed, as all pins are input anyway.

That's how SRAMs are wired on EVERY Nintendo made board that have them (all least every standard ones).

I understand that it works, but Nintendo doesn't always do it the "right" way, they do it the cheapest way such as bulk 74161 as 4-bit registers and the /ROMSEL signal which relies entirely on relatively fast asynchronous memory and doesn't let you recover A15 at Phi1.

And positive CE is also present on 128 KB SRAMs, but lacks in 32 KB and 2 KB SRAMs.

And practically all other SRAM, DRAM and PROM chips. Again it's not a "bad" thing, just not universally compatible.

And I don't know what you are talking about bus conflicts. As long RAM is only enabled for $6000-$7ffff, there cannot be any bus conflicts, since nothing else is mapped here.

I was talking about preventing $8000-FFFF conflicts at mapper writes, not SRAM ;)

Edit: After some brain crunching I found that only 5 NAND2s instead of 6 could be used to preform the logic I posted above and consequently that a single 7410 could be used too! It's only ~$0.10 more than 7400, ~$0.05 more than 7408 but it can properly decode any memory to $6000, and allow for setup times, and reconstruct /RD and /WR to remove mapper busconflicts:

[tepples]

Edit: After some brain crunching I found that only 5 NAND2s instead of 6 could be used to preform the logic I posted above and consequently that a single 7410 could be used too! It's only ~$0.10 more than 7400, ~$0.05 more than 7408 but it can properly decode any memory to $6000, and allow for setup times, and reconstruct /RD and /WR to remove mapper busconflicts:

The "+5V" signals can be replaced with another copy of PHI2, right? It'd look like this:

Code: Select all

NES cart edge                  RAM

              ____
/ROMSEL -----|    `-.
             |       \
A14 ---------|        )o------ /CS
             |       /
A13 ---------|____,-'

              ____
R/W ---------|    `-.
             |       \
Phi2 -----+--|        )o--+--- /OE
          |  |       /    |
          +--|____,-'     |
          |               |
          |   ____        |
          +--|    `-.     |
          |  |       \    |
          +--|        )o--(--- /WE
             |       /    |
          ,--|____,-'     |
          |               |
          `---------------'

But what would we call the board that's equivalent to UNROM or UOROM but has SRAM? And what additional circuitry would we need for a battery-backed SRAM?

[Bregalad]

But what would we call the board that's equivalent to UNROM or UOROM but has SRAM?

Unless someone figured out the logic Nintendo employed for the second letter of board names, or find out an obscure japanse game that uses a board like this and that noone know of it right now, we'll never know.

And what additional circuitry would we need for a battery-backed SRAM?

A battery backup controller, there exist a couple of sort, with both positive and negative chip enable inputs (altrough those with negative seems more common).
Alternatively, a battery backed 74HCU04 (or equivalent chip) would do the trick, along with the clasical diode/resistor circuit on the VCC of both the SRAM and the HCU04 chip. Someone who feels experimental could try doing it's own mosfet inverter, which should work, but I guess it would drain much more current from the battery as opposed to integreated circuit made for it.

[kyuusaku]

The "+5V" signals can be replaced with another copy of PHI2, right?

Sure, I put +5V because I think it's negligibly faster and shows that only 2 inputs are really used.

And what additional circuitry would we need for a battery-backed SRAM?

Here is where the extra /WR input can come in handy, since with a working /RESET (Phi2-diode-RC?) it should block writes at hard reset.

[Bregalad]

Sure, I put +5V because I think it's negligibly faster and shows that only 2 inputs are really used.

Yeah, also most times the circuit is easier to route if 2 adjacent pins are just wired together, as opposed to if you have to route a power supply to a input pin where you'd want other signals to pass. In some particular cases it may be the other way arround if both inputs aren't neigtboor pins.

Here is where the extra /WR input can come in handy, since with a working /RESET (Phi2-diode-RC?) it should block writes at hard reset.

Yeah, that would rock, however it doesn't block the chip when the power is going down (which is the main source of SRAM corruption if I'm not mistaking), so another circuit would be needed for that.