adding WRAM to N/CN dev-cart

crazyness · Post by **crazyness** » Fri Dec 31, 2010 1:06 pm

I read you can add WRAM at $6000-$7FFF
thinking about some to my dev cart

how would I go about it?

Post by **tepples** » Fri Dec 31, 2010 3:12 pm

The last time we tried this, it ended up on this page. I don't know whether kyuusaku's final suggestion is vulnerable to corruption due to $E000-$FFFF writes or not.

crazyness · Post by **crazyness** » Fri Dec 31, 2010 7:37 pm

the family basic cart used 74ls20 dual 4-input NAND gate
looking at the board scans in the database seems it only used half the chip
but it also looks like it had a write protect switch

is basic the only cartridge that used battery backed WRAM without a custom mapper chip?

kyuusaku · Post by **kyuusaku** » Fri Dec 31, 2010 10:12 pm

For 74LS20:

A = Phi2
B = /ROMSEL
C = A14
D = A13

Y = WRAM /CE

WRAM /OE = GND
WRAM /WE = switched between VCC and R//W

You could also use the other gate to invert R//W and use that for /OE (for /OE on the ROM too to prevent bus conflicts).

crazyness · Post by **crazyness** » Sat Jan 01, 2011 7:33 am

seems like it would work and wouldn't prevent writing to $8000-$FFFF

just to confirm your suggestion

1A = Phi2
1B = /ROMSEL
1C = A14
1D = A13
1Y = WRAM /CE

2A = R/W
2B = Vcc
3C = Vcc
2D = Vcc
2Y = PRG /OE

did you try this out yourself?

Drag · Post by **Drag** » Thu Mar 24, 2011 10:23 am

tepples wrote:The last time we tried this, it ended up on this page. I don't know whether kyuusaku's final suggestion is vulnerable to corruption due to $E000-$FFFF writes or not.

Sorry for the topic necro, but I just came across that wiki page yesterday.

Yes, there's a race condition between M2 and PRG /CE, but wouldn't the most viable workaround for that be to simply not have your mapper's registers mapped at C000-FFFF? Writes between 8000-BFFF would only coincide with addresses 0000-3FFF, which are entirely off limits to the cartridge anyway, so there's no possible way for a write within that region to cause a conflict.

The only other possible workaround I can think of is to assume SYSTEM CLK will pulse before M2 toggles, and use that to trigger a write to the RAM on the falling edge of M2, where PRG /CE and M2 are both (theoretically) stable. However, I dunno if that's how it works. (plus, this wouldn't be available on the famicom)