Cx4 Pinout

[qwertymodo]

Well, all I know is that pin 61 on the Cx4 connects to pin 18 on the cart edge.

[koitsu]

Well, all I know is that pin 61 on the Cx4 connects to pin 18 on the cart edge.

If it's anything like the SA-1, it probably uses this as a "trigger" to inform software running on the main SNES CPU when a particular "thing" has completed.

[qwertymodo]

Well, all I know is that pin 61 on the Cx4 connects to pin 18 on the cart edge.

If it's anything like the SA-1, it probably uses this as a "trigger" to inform software running on the main SNES CPU when a particular "thing" has completed.

You just defined interrupt requests in fine /r/ELI5 fashion

[Near]

Neat. If it has IRQ functionality, it'll most likely be tied to the HALT instruction. Aside from code in SNES WRAM constantly reading that register, that'd be the only way to know when the Cx4 finishes executing, since Cx4 programs have to take over the ROM chip.

Its status is returned in $7f5f twice, so one of those bits is probably an IRQ acknowledge.

The IRQ enable bit would most likely reside in $7f48, 7f4c, 7f50, 7f51 or 7f52. Most likely, it is not 7f52, as that configures the number of ROMs selectable. Based on the number of bits assignable, $7f48 or 7f51 are the most likely candidates.

If it's there, I'll find it with the dev cart =)

[qwertymodo]

Well, I'm pretty comfortable calling pin 25 SRAM /CE with this. Reads and writes across the full $70-7F:0000-FFFF address space pull pin 25 low, then strobe pin 51 or 52 accordingly. Down to 2 unknowns.

[qwertymodo]

Well, now that I have that all figured out, the next step is to build a from-scratch Cx4 dev board, with 2x16Mbit ROMs (though realistically 1x16Mbit + 1x8Mbit is all that's really useable...) and 256Kbit SRAM. Since I know the /CE pins get held low and don't toggle, I'm including an optional footprint for a 74*00 configured to decode a toggled /CS for non-volatile F-RAM instead of the SRAM. Or, if you prefer traditional SRAM, I'm also including footprints for a battery and a DS1312 NVRAM controller. With pins 74 and 75 unknown, I'm thinking I'll connect them each to Gnd through a solder jumper, so they can be disconnected if so desired. I may make it a 2-way jumper to Vcc or Gnd if I come across any indication that such a thing might be useful.

[nocash]

Just found another CX4 pinout document: http://cgfm2.emuviews.com/new/cx4tech.txt
It does have some missing pins, too. The pins marked "Likely A15,A16,A17,A18,A19" may be wrong. The two /RCS pins, /ROE and /IRQ are looking good. And well, look for yourself what is same/different.
Oh, but one very basic different thing: The cx4tech.txt file lists Pin 66 as Ground (not VCC).

[qwertymodo]

Pin 66 connects to a short trace into a pair of vias that connect right in the middle of a fill plane on the back of the board connected to pin 27 on the cart edge. On RMX2, there's also a decoupling capacitor to Gnd, which may have been why that document listed it as being connected to Gnd, if they didn't understand the purpose of the decoupling capacitor and just traced it from the Gnd side of the capacitor, then it would have looked like it was connected to Gnd. But it's definitely Vcc, and based on a few geometry decisions on RMX3, as well as the decoupling cap on RMX2, I'm fairly confident it's a supply pin, not just a digital input pulled high by connecting it to Vcc. Again, I don't currently have a chip desoldered, so I can't check the Vcc/Gnd pins for internal connections, but that would be the easy way to know for sure.

Edit: Many of the differences between that document and mine are due to the pinout he used for the MaskROM. Take a look at this thread where they're discussing exactly that same issue. You can see from the fact that he wrote down the pin number that it matches up completely with my tracing of RMX2 here, he just used an incorrect MaskROM pinout for determining what to name the signals. I believe he has a typo for pin 52, because he says it connects to ROM pin 3, but calls it A18, then look at pin 33, also ROM pin 3, but he calls it A15. He probably meant ROM pin 31 for Cx4 pin 52. SNES MaskROMs, even those labeled LH538/LH534, do NOT share the same pinout as the Sharp LH538 datasheet. This is where the logic analyzer/functional testing comes in, because continuity testing requires reliable pinouts for all of the other devices in order to understand what they're connected to. I've only really done logic analysis on the control pins (the various /CE's, /OE's, and /WE's), however, the fact that I was able to program a ROM before mounting it to the board and the game ran correctly gives me a lot of confidence that my address lines are all assigned correctly. Same goes for the flash ROM program sequence, which requires writing to several specific addresses on the ROM, and wouldn't work properly if the ROM's pins had been swapped around like is sometimes done for EEPROM repros.