SPC700 Opcode Matrix

[jwdonal]

Would anyone be interested in an opcode matrix for the SPC700 instruction set? I made some in multiple formats to help me understand the organization of the opcodes when I write my emu. Here are some low-res examples of a few of them just to give you an idea. I plan on making some more as well.

Group by Type
Group by Address Mode
Group by Bits

If anyone is interested I can post some hi-res versions somewhere.

Are things like this already available for the SPC700? There are lots of them for 6502/65816, but I couldn't find any for SPC700 so that's why I made these.

[doppelganger]

Those are too low-res to be useful. The text is too small to read.

[blargg]

Would anyone be interested [...] Here are some low-res examples of a few of them just to give you an idea.

[KungFuFurby]

That's not a bad idea, actually. I actually haven't seen matrixes for the majority, if not all of the assembly languages... so I would be interested in seeing one for the SPC700.

[doppelganger]

Would anyone be interested [...] Here are some low-res examples of a few of them just to give you an idea.

I could not read the text in the low-res versions because it was too small, so yeah you should definitely make some higher-res versions real soon.

I could, however, read the text in the original post just fine, blargg. :-/

[jwdonal]

Sure I can post 'em. Won't be able to until later tonight though.

That's not a bad idea, actually. I actually haven't seen matrixes for the majority, if not all of the assembly languages... so I would be interested in seeing one for the SPC700.

Sorry for not responding to ur post. I either didn't get a notification email or I deleted it by accident thinking it was for another post that I had already replied to.

[jwdonal]

Here are the opcode matrices that I created. Feedback/corrections are very welcome. Enjoy!

SPC700 Opcode Matrix by Type (Native Mnemonics)
SPC700 Opcode Matrix by Type (65816-Style Mnemonics)
SPC700 Opcode Matrix by Addressing Mode (Native Mnemonics)
SPC700 Opcode Matrix by Addressing Mode (65816-Style Mnemonics)
SPC700 Opcode Matrix by Bits (Native Mnemonics)
SPC700 Opcode Matrix by Bits (65816-Style Mnemonics)
SPC700 Addressing Modes Effective Address Regions

You can also find them here.

[tepples]

In #nesdev, doppelganger said he was trying to come up with his own take on 65C02-style mnemonics for the rest of the instructions, especially PSR and TSR instead of PCALL and TCALL. And the I flag mechanics are opposite from 65C02; doppelganger's solution mirrors jwdonal's (exchange the mnemonics).

Code: Select all

    x0   x1    x2    x3    x4   x5    x6    x7     x8    x9      xA      xB   xC   xD    xE    xF

0x  NOP  TSR   SMB0  BBS0  ORA  ORA   ORA   ORA    ORA   OR      OR1     ASL  ASL  PHP   TSB   BRK
         0     n     n,d   n    nn    (X)   (n,X)  #n    nd,ns   C,nn.b  n    nn         nn

1x  BPL  TSR   RMB0  BBR0  ORA  ORA   ORA   ORA    OR    OR      DECW    ASL  ASL  DEX   CPX   JMP
    d    1     n     n,d   n,X  nn,X  nn,Y  (n),Y  n,#n  (X),(Y) n       n,X  A          nn    (nn+X)

2x  CLP  TSR   SMB1  BBS1  AND  AND   AND   AND    AND   AND     OR1     ROL  ROL  PHA   CBNE  BRA
         2     n     n,d   n    nn    (X)   (n,X)  #n    nd,ns   C,/nn.b n    nn         n,d   d

3x  BMI  TSR   RMB1  BBR1  AND  AND   AND   AND    AND   AND     INCW    ROL  ROL  INX   CPX   JSR
    d    3     n     n,d   n,X  nn,X  nn,Y  (n),Y  n,#n  (X),(Y) n       n,X  A          n     nn

4x  SEP  TSR   SMB2  BBS2  EOR  EOR   EOR   EOR    EOR   EOR     AND1    LSR  LSR  PHX   TRB   PSR
         4     n     n,d   n    nn    (X)   (n,X)  #n    nd,ns   C,nn.b  n    nn         nn    u

5x  BVC  TSR   RMB2  BBR2  EOR  EOR   EOR   EOR    EOR   EOR     CMPW    LSR  LSR  TAX   CPY   JMP
    d    5     n     n,d   n,X  nn,X  nn,Y  (n),Y  n,#n  (X),(Y) YA,n    n,X  A          nn    nn

6x  CLC  TSR   SMB3  BBS3  CMP  CMP   CMP   CMP    CMP   CMP     AND1    ROR  ROR  PHY   DBNZ  RTS
         6     n     n,d   n    nn    (X)   (n,X)  #n    nd,ns   C,/nn.b n    nn         n,d

7x  BVS  TSR   RMB3  BBR3  CMP  CMP   CMP   CMP    CMP   CMP     ADDW    ROR  ROR  TXA   CPY   RTI
    d    7     n     n,d   n,X  nn,X  nn,Y  (n),Y  n,#n  (X),(Y) YA,n    n,X  A          n

8x  SEC  TSR   SMB4  BBS4  ADC  ADC   ADC   ADC    ADC   ADC     EOR1    DEC  DEC  LDY   PLP   MOV
         8     n     n,d   n    nn    (X)   (n,X)  #n    nd,ns   C,nn.b  n    nn   #n          n,#n

9x  BCC  TSR   RMB4  BBR4  ADC  ADC   ADC   ADC    ADC   ADC     SUBW    DEC  DEC  TSX   DIV   XCN
    d    9     n     n,d   n,X  nn,X  nn,Y  (n),Y  n,#n  (X),(Y) YA,n    n,X  A          YA,X  A

Ax  SEI  TSR   SMB5  BBS5  SBC  SBC   SBC   SBC    SBC   SBC     MOV1    INC  INC  CPY   PLA   STA
         10    n     n,d   n    nn    (X)   (n,X)  #n    nd,ns   C,nn.b  n    nn   #n          (X)+

Bx  BCS  TSR   RMB5  BBR5  SBC  SBC   SBC   SBC    SBC   SBC     MOVW    INC  INC  TXS   DAS   LDA
    d    11    n     n,d   n,X  nn,X  nn,Y  (n),Y  n,#n  (X),(Y) YA,n    n,X  A                (X)+

Cx  CLI  TSR   SMB6  BBS6  STA  STA   STA   STA    CPX   STX     MOV1    STY  STY  LDX   PLX   MUL
         12    n     n,d   n    nn    (X)   (n,X)  #n    nn      nn.b,C  n    nn   #n          YA

Dx  BNE  TSR   RMB6  BBR6  STA  STA   STA   STA    STX   STX     MOVW    STY  DEY  TYA   CBNE  DAA
    d    13    n     n,d   n,X  nn,X  nn,Y  (n),Y  n     n,Y     n,YA    n,X             n+X,d

Ex  CLV  TSR   SMB7  BBS7  LDA  LDA   LDA   LDA    LDA   LDX     NOT1    LDY  LDY  NOTC  PLY   SLEEP
         14    n     n,d   n    nn    (X)   (n,X)  #n    nn      nn.b    n    nn         

Fx  BEQ  TSR   RMB7  BBR7  LDA  LDA   LDA   LDA    LDX   LDX     MOV     LDY  INY  TAY   DBNZ   STOP
    d    15    n     n,d   n,X  nn,X  nn,Y  (n),Y  n     n,Y     nd,ns   n,X             Y,d

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