6502 Illegal Opcodes

[WedNESday]

I cannot get the following to work in my emulator even if I follow the following guide VERY accurately;

http://www.ataripreservation.org/websit ... lopc31.txt

ARR
ATX
AXS
DCP
ISC
RRA
SXA
SYA

Can somebody please check the above document and tell me if it is accurate or not and if not please provide any corrections. All of the CPU test ROMs that I have tried give error codes that don't tell you what is actually wrong with your emulation.

[tepples]

Any unofficial opcode not listed on this page probably need not be implemented.

ARR is AND #imm ROR A, with different flags.
ATX varies based on ambient temperature and RF and is discouraged. Probably nothing but test ROMs uses it.
AXS is X = (A AND X) - imm
DCP is DEC addr then CMP addr
ISC is INC addr then SBC addr
RRA is ROR addr then ADC addr
SXA, also called SHX, stores X AND ((address >> 8) + 1) at the address. Probably nothing but test ROMs uses it.
SYA, also called SHY, stores Y AND ((address >> 8) + 1) at the address. Probably nothing but test ROMs uses it.

[WedNESday]

I've fixed AXS now. Even if no game actually uses it, I still want to emulate it. Test ROMs will fail if I don't and its still NES behaviour.

The problem is, when to set the flags? For instance, RRA fetches the byte from memory, rotates it right 1 bit and then performs ADC on it setting the flags like ADC normally does. Yet it still fails. Are any of the flags only modified during that rotate right?

[tepples]

I've fixed AXS now. Even if no game actually uses it, I still want to emulate it.

I plan to use it for sprites.

The problem is, when to set the flags? For instance, RRA fetches the byte from memory, rotates it right 1 bit and then performs ADC on it setting the flags like ADC normally does. Yet it still fails. Are any of the flags only modified during that rotate right?

N and Z come out of the ROR, but C and V come out of the odd mixture of ADC and AND.

[Movax12]

AXS is a great instruction.

Code: Select all

; move all sprites offscreen
ldx #$00
lda #$FF
loop:
    sta $0200, x
    axs #<-$04
bne loop

[thefox]

AXS is a great instruction.

Code: Select all

; move all sprites offscreen
ldx #$00
lda #$FF
loop:
    sta $0200, x
    axs #<-$04
bne loop

That's a really nice trick, I'm going to have to steal that one.

[WedNESday]

N and Z come out of the ROR, but C and V come out of the odd mixture of ADC and AND.

And I have done what the document in my first post does exactly and still no luck.

Code: Select all

	A &= DataBus;
	N = Z = A >>= 1;

	switch (A & 0x60)
	{
		case 0x00:
			V = 0x00;
			C = 0x00;
			break;
		case 0x20:
			V = 0x40;
			C = 0x00;
			break;
		case 0x40:
			V = 0x40;
			C = 0x01;
			break;
		case 0x60:
			V = 0x00;
			C = 0x01;
			break;
	}

What gets me is that that is the only document on the internet which actually addresses 6502 illegal opcodes. None of the browser emulators I could find emulated any of the illegal opcodes.

[tepples]

I'm pretty sure Visual 6502 does the unofficial opcodes, given that it's a transistor-level simulation of the original silicon.

[WedNESday]

I'm pretty sure Visual 6502 does the unofficial opcodes, given that it's a transistor-level simulation of the original silicon.

According to Visual 6502, C is the lowest bit of A before the shift right which is not what that other document says. Also Visual 6502 doesn't set the V flag during the operation. So now we have 2 conflicting statements.

[WedNESday]

ARR = AND + ROR as opposed to AND + LSR as I had been treating it. Thanks to Nestopia's source code for the fix.

ATX, according to the document says AND A with Immediate and transfer to X. Nestopia says load A and X with immediate value. blargg's test ROM agrees with Nestopia both times.

[lidnariq]

ATX is one of the instructions in the analog feedback zone, although comparatively well behaved. It is the intersection of TAX and LDA #immed, so it's something like:

Simultanously:
* Drive SB with value from RAM/ROM
* Drive SB with value of A
* Load A with value from SB
* Load X with value from SB

The first two have an AND effect, that's definitely correct. The 2nd and 3rd are the analog feedback trap; like in XAA it means that the six bits of $EE will all act the same, and two bits of $11 will all act the same, but both groups may not act the same.

I'd bet it'll do something wonky if a DPCM read intersects with it.

[WedNESday]

Yeah, I wondered if some opcodes would vary from machine to machine or be analogue.

ISC

Code: Select all

DataBus++;
DataBus ^= 0xFF;
ADC();

For some reason the above code fails on all test ROMs that I have tried. Even though ADC works for certain and inverting the DataBus beforehand to emulate SBC also works.

[tepples]

ISC means you do the whole INC before the subtraction, including writeback.

[WedNESday]

ISC means you do the whole INC before the subtraction, including writeback.

Writeback? If you mean the write to memory that is done, I merely omitted it above.

[WedNESday]

Only need to do SXA and SYA now. According to Nestopia's source code, you AND X with the high byte of the target address + 1 and this sets the address rather than the value of the databus itself.

Address = (X & (High + 1));

and not

Databus = (X & (High + 1));

Is this correct?