About 2A03 technical reference

[Boolean]

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|* \/ |
ROUT <01] [40< VCC
COUT <02] [39> $4016W.0
/RES >03] [38> $4016W.1
A0 <04] [37> $4016W.2
A1 <05] [36> /$4016R
A2 <06] [35> /$4017R
A3 <07] [34> R/W
A4 <08] [33< /NMI
A5 <09] [32< /IRQ
A6 <10] 2A03 [31> PHI2
A7 <11] [30< ---
A8 <12] [29< CLK
A9 <13] [28] D0
A10 <14] [27] D1
A11 <15] [26] D2
A12 <16] [25] D3
A13 <17] [24] D4
A14 <18] [23] D5
A15 <19] [22] D6
VEE >20] [21] D7
|________|
CLK: this is the 2A03's master clock input line (236250/11 KHz), and clocks
an internal divide-by-12 counter.
PHI2: this output is the divide-by-12 result of the CLK signal (1.79 MHz).
An internal clock edge divider of 14915 off the 2A03's PHI2 line is used to get 240Hz.
==============================================================
What I can't understand is 1.79MHz / 14915 = 120Hz not 240Hz.
Is my understanding wrong?
Help, please.

[lidnariq]

If possible, please use the wiki ( http://wiki.nesdev.com ) instead of the documents on the root ( http://nesdev.com/2A03%20technical%20reference.txt ) — some of the older stuff is wrong, and we don't have a way of editing it.

In this case, http://wiki.nesdev.com/w/index.php/APU_Frame_Counter

[Boolean]

If possible, please use the wiki ( http://wiki.nesdev.com ) instead of the documents on the root ( http://nesdev.com/2A03%20technical%20reference.txt ) — some of the older stuff is wrong, and we don't have a way of editing it.

In this case, http://wiki.nesdev.com/w/index.php/APU_Frame_Counter

Thank you, I really should head for here.