How to understanding APU status register $4015

[Boolean]

Question A
$4015 IF-D NT21
$4017 MI-- ----
Focus only on $4015.D6 and $4017.D6.
1. If $4017.D6 is 0, when read $4015, then $4015.D6 return 0 and $4015.D6 set 1.
2. If $4017.D6 is 0, when read $4015, then $4015.D6 return 1 and $4015.D6 set 0.
3. If $4017.D6 is 1, when read $4015, then $4015.D6 return 0 and $4015.D6 set 1.
4. If $4017.D6 is 1, when read $4015, then $4015.D6 return 1 and $4015.D6 set 0.
Which two are right?

Question B
Assume 4015.D0 is set and $4000.D5(length counter halt) is set.
Write $4003, whether reload length counter or not?
Thanks.

[Quietust]

Question A
$4015 IF-D NT21
$4017 MI-- ----
Focus only on $4015.D6 and $4017.D6.
1. If $4017.D6 is 0, when read $4015, then $4015.D6 return 0 and $4015.D6 set 1.
2. If $4017.D6 is 0, when read $4015, then $4015.D6 return 1 and $4015.D6 set 0.
3. If $4017.D6 is 1, when read $4015, then $4015.D6 return 0 and $4015.D6 set 1.
4. If $4017.D6 is 1, when read $4015, then $4015.D6 return 1 and $4015.D6 set 0.
Which two are right?

Reading $4015 returns D6=1 when there is an active Frame IRQ (and also acknowledges the interrupt, causing subsequent reads to give D6=0), and Frame IRQs can only occur when both $4017.D6 and $4017.D7 are 0 (in which case they occur approximately once per frame).

Question B
Assume 4015.D0 is set and $4000.D5(length counter halt) is set.
Write $4003, whether reload length counter or not?

The length counter is reloaded whether the "halt" flag is set or clear.

[Boolean]

Question A confusing me a long time.
Thank you for your answer.

[Boolean]

Reading $4015 returns D6=1 when there is an active Frame IRQ (and also acknowledges the interrupt, causing subsequent reads to give D6=0), and Frame IRQs can only occur when both $4017.D6 and $4017.D7 are 0 (in which case they occur approximately once per frame).

Whether the CPU will be generated Frame IRQs by the APU
when both $4017.D6 and $4017.D7 are 0, but the CPU status register(its D3 == 1) disables IRQ?

[Bregalad]

While physically the sound hardware and the CPU are in the same chip, they are separate components internally.

The APU will still generate the IRQ, as it doesn't have a clue about the I flag of the 6502.
Similarly, the 6502 will ignore the IRQ because the I flag is set, no matter if the IRQ comes from the APU or the cartridge (or whatever else), because it just knowns that the "IRQ" signal is low, but doesn't know who causes it.

This applies to both frame IRQs and DMC IRQs, too.

[Boolean]

The APU will still generate the IRQ, as it doesn't have a clue about the I flag of the 6502.
Similarly, the 6502 will ignore the IRQ because the I flag is set, no matter if the IRQ comes from the APU or the cartridge (or whatever else), because it just knowns that the "IRQ" signal is low, but doesn't know who causes it.

When the 6502 ignores an Frame IRQ only because of I flag, does the $4015.D6 set to 1?

[rainwarrior]

Yes, the $4015 IRQ flag (and the IRQ assertion itself) will operate the same whether or not the I flag is set.

When the I flag is set, the IRQ line still gets asserted, it just doesn't branch to the IRQ vector unless the I flag is clear. If you haven't read $4015 to clear it and its IRQ flag is still on when you happen to CLI, it will immediately branch to the IRQ.

[Boolean]

Thank you

[Boolean]

When $4015 is read, the status of the channels' length counters and bytes
remaining in the current DMC sample, and interrupt flags are returned.
Afterwards the Frame Sequencer's frame interrupt flag is cleared.

Afterwards the Frame Sequencer's frame interrupt flag is cleared means bit 6 of register $4017 is SET to disable frame IRQs?

[rainwarrior]

No. That is a different flag.

When the IRQ happens, the IRQ flag bit in $4015 is set and will remain set until you read it. If the CPU is not masking IRQ signals (i.e. depending on the use of sei/cli instructions) the CPU will receive an IRQ signal while this bit is set.

$4017's IRQ inhibit flag will prevent the operation of the IRQ flag bit in $4015, but reading $4015 does not set the IRQ inhibit flag in $4017.

[Boolean]

Thank you. Reading or writing $4015 never impact each bit of $4017. The frame IRQ occured($4017 wrote with %00xx xxxx) flag is set at $4015.D6 only and its clearing is in reading $4015.
When the $4015.D6 is set, we write a $80 or $40 to $4017, so if the $4015.D6 will be cleared